[help] pt's error when read sdf

[iamczx]

pte-014 pt

##Worst case working condition
read_sdf  /direct/sh-home/kevin.sheng/design/809_i2c/layout/2006_0104_from_layout/pmp_dig_slow.sdf -type sdf_max
Warning: The SDF file is version 3.0. Current SDF-3.0 
	 supported constructs are: REMOVAL, RECREM, RETAIN and CONDELSE. (SDF-026)
Error: No net timing arc from pin 'a/Y' to pin 'core/b/CK'. (PTE-014)
Error: No net timing arc from pin 'a/Y' to pin 'core/c/CK'. (PTE-014)

Then I check the verilog code , and find that a/y to core/b/ck Or a/y to core/c/Ck
is set as false_path by front_end constrant.
How should I do to fix such errors?
thanks

 

[ami]

verilog pt sdf

##Worst case working condition
read_sdf  /direct/sh-home/kevin.sheng/design/809_i2c/layout/2006_0104_from_layout/pmp_dig_slow.sdf -type sdf_max
Warning: The SDF file is version 3.0. Current SDF-3.0 
	 supported constructs are: REMOVAL, RECREM, RETAIN and CONDELSE. (SDF-026)
Error: No net timing arc from pin 'a/Y' to pin 'core/b/CK'. (PTE-014)
Error: No net timing arc from pin 'a/Y' to pin 'core/c/CK'. (PTE-014)

Then I check the verilog code , and find that a/y to core/b/ck Or a/y to core/c/Ck
is set as false_path by front_end constrant.
How should I do to fix such errors?
thanks

1.May be your netlist is different from your sdf. check to see if these path exist
2.May be the "set_false_path -from a/Y to core/b/Ck" in your PT script cause the ERROR. after synthesis, the path name may not be the same with the path in verilog code.
rgrds

 

[jjww110]

i think the pin name has been changed!!

 

[leeenghan]

Hi,

In the sdf, there is a net delay from instant a pin Y to instance core/b pin ck.

When you read the sdf, these net connection does not exist. I don't think it has anything to do with false path. Check you design flow that the sdf is meant for the netlist you read into PT.


Regards,
Eng Han

 

[iamczx]

now I am doubt that it is the lib cell cause the error.
the clock buffer : input ck, output c and cn, It has 2 output,therefore, the soc tell me that the buffer has 2 timing arc when cts.
And all the clock buffer has 2 output pin in lib. So the apr enginner use common buffer to do apr.
anyone give more advice ? thanks

 

[iamczx]

There are some errors exisiting in the verilog code after re-checking the verilog code.Thx all