entity score is
port(
load :in std_logic;
clk,up,dn,en1,en2:in std_logic;
scorein :in std_logic_vector(3 downto 0);
scoreout
ut std_logic_vector(3 downto 0)
);
end score;
architecture behave of score is
signal temp :std_logic_vector(3 downto 0);
begin
process(load,clk)
begin
temp <=scorein;
if load='1' then.............................................. ..........18
temp <="0101";
elsif clk'event and clk='1' then....................................20
if up='1' and en1='1' and en2='1' then
if temp="1001" then
null;
else
temp <=temp+1;
end if;
elsif dn='1' and en1='1' and en2='1' then
if temp="0000" then
null;
else
temp <=temp-1;
end if;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = 1 then
scoreout<=temp;
end if
endprocess
end behave;
--The above code can re-write as
-- added a rst signal(which is must for any counter)
architecture rtl of score is
signal temp : std_logic_vector(3 downto 0)
begin
process(rst,clk)
begin
if ( rst = '0) -- active low reset
temp < (others => '0');
else if clk'event and clk = '1' then
if load = '1' then
temp <= "0101";
elsif (en1 = '1' and en2 = '1') then
if (up = '1' and temp != "1001") then
temp <= temp + '1' ;
elsif (dn = '1' and temp != "0000" ) then
temp <= temp - '1' ;
end if;
end if;
end if;
endprocess
process(clk)
begin
if clk'event and clk = 1 then
scoreout<=temp;
end if
endprocess
end rtl;
-- Please check for syntax
-- Read any coding guidelines before you start coding..it is always good to read at the begining...as you get exp you will not do the mistake
best of luck
Shyam
Caution : Never use variable, this will lead to
---------- Post added at 05:42 ---------- Previous post was at 05:42 ----------
Synthesi and simulation mismatches... the hardware infere when variable used lead to many confusion more ever it is visible within the process
---------- Post added at 05:45 ---------- Previous post was at 05:42 ----------
add this after the process begin, forgot to add it
"temp <=scorein;":wink: