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Help:problems with VHDL,wish someone help me solve it

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sispyhus

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some problems with VHDL.I have checked it for many times,but Quartus always report the mistakes.i would appreciate it if you can help me.
the code as follows:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity score is
port(load:in std_logic;
clk,up,dn,en1,en2:in std_logic;
scorein:in std_logic_vector(3 downto 0);
scoreout:eek:ut std_logic_vector(3 downto 0));
end score;

architecture behave of score is
begin
process(load,clk)
variable temp:std_logic_vector(3 downto 0);
begin
temp:=scorein;
if load='1' then........................................................18
temp:="0101";
elsif clk'event and clk='1' then....................................20
if up='1' and en1='1' and en2='1' then
if temp="1001" then
null;
else
temp:=temp+1;
end if;
elsif dn='1' and en1='1' and en2='1' then
if temp="0000" then
null;
else
temp:=temp-1;
end if;
end if;
end if;
scoreout<=temp;
end process;
end behave;

..........................................................
the mistakes :
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[0] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[1] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[2] because it does not hold its value outside the clock edge
Error (10818): Netlist error at SCORE.vhd(18): can't infer register for temp[3] because it does not hold its value outside the clock edge
Error (10822): HDL error at SCORE.vhd(20): couldn't implement registers for assignments on this clock edge
Error: Can't elaborate user hierarchy "score4:45|SCORE:1"
 

lucbra

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make temp a signal in stead of a variable in a process.

it will solve your problems
 

sispyhus

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I have changed the code as you said,but it doesn't work.

Could you tell me how to change in detail,please?
 

permute

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It probably has something to do with score out being assigned outside of the main if-else block, as well as temp being assigned outside. most likely the latter. try moving the temp=scorein line to be inside the clocked portion.
 

shyam4908

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entity score is
port(
load :in std_logic;
clk,up,dn,en1,en2:in std_logic;
scorein :in std_logic_vector(3 downto 0);
scoreout :eek:ut std_logic_vector(3 downto 0)
);
end score;

architecture behave of score is
signal temp :std_logic_vector(3 downto 0);
begin
process(load,clk)
begin
temp <=scorein;
if load='1' then.............................................. ..........18
temp <="0101";
elsif clk'event and clk='1' then....................................20
if up='1' and en1='1' and en2='1' then
if temp="1001" then
null;
else
temp <=temp+1;
end if;
elsif dn='1' and en1='1' and en2='1' then
if temp="0000" then
null;
else
temp <=temp-1;
end if;
end if;
end if;
end process;

process(clk)
begin
if clk'event and clk = 1 then
scoreout<=temp;
end if
endprocess
end behave;

--The above code can re-write as
-- added a rst signal(which is must for any counter)

architecture rtl of score is
signal temp : std_logic_vector(3 downto 0)
begin
process(rst,clk)
begin
if ( rst = '0) -- active low reset
temp < (others => '0');
else if clk'event and clk = '1' then
if load = '1' then
temp <= "0101";
elsif (en1 = '1' and en2 = '1') then
if (up = '1' and temp != "1001") then
temp <= temp + '1' ;
elsif (dn = '1' and temp != "0000" ) then
temp <= temp - '1' ;
end if;
end if;
end if;
endprocess

process(clk)
begin
if clk'event and clk = 1 then
scoreout<=temp;
end if
endprocess

end rtl;

-- Please check for syntax
-- Read any coding guidelines before you start coding..it is always good to read at the begining...as you get exp you will not do the mistake

best of luck
Shyam

Caution : Never use variable, this will lead to

---------- Post added at 05:42 ---------- Previous post was at 05:42 ----------

Synthesi and simulation mismatches... the hardware infere when variable used lead to many confusion more ever it is visible within the process

---------- Post added at 05:45 ---------- Previous post was at 05:42 ----------

add this after the process begin, forgot to add it

"temp <=scorein;":wink:
 

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