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Help plz: How to KEEP cell and prevent it being optimized?

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Alfred_zhang

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xst (* keep = true *)

Hi, thanks for your attention.

Do you know how to keep some logic and prevent it from being optimized by the XST? For example I want to delay the clk by adding two extra NOT gate. How to KEEP the two NOT gate? And where and how to see the synthesize result to make sure these cells are not optimized by the tool?

Thanks
 

echo47

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Try the "KEEP" constraint. This works in ISE 9.1.03i with Spartan-3:
Code:
module top (in, out);
  input in;
  (* KEEP="TRUE" *) wire [6:0] delay;     // several delays
  output out;

  assign {out,delay} = ~{delay,in};
endmodule
If I use buffers instead of inverters, XST optimizes them away despite the KEEP constraint. Maybe an XST bug.

I use FPGA Editor to view the layout to be sure the items haven't been optimized away.

Delaying an FPGA clock with gates sounds dubious. You don't have much control over the delay time.
 

Alfred_zhang

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Thanks, Echo47!

I will make a try in your way.

and I find that maybe the Primitive IDELAY is helpful too.

To see the netlist have to wait until PAR complete?
 

echo47

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IDELAY can be very handy. It's certainly more predictable than gate/routing delays.

Yes, I use FPGA Editor to view the routed chip after PAR finishes. I haven't tried viewing any intermediate files. I figured they may not include all the optimizations. I'm not sure, though.
 

Alfred_zhang

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Hi, Echo47:
I mad a try in your "KEEP" way, it's OK. The inverters didn't been optimized.
I fonud that invoking the "generate post synthesize simulate module" will generate a netlist file(*.v), here we can see the synthesize results.
and in my try, the inverter didn't be optimized in the follow map/PAR process.
Of couse, view *.ncd file is the best way to make sure.
Learned a lot after u.
Thanks and best regards!
 

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