Help PLZ!! FPGA Clock
At least you have to remove clk2 <= 0, it's causing a multiple source error otherwise. The reg clk2 can be set in one always block only. Missing endmodule is another issue of course. You showed just some snippets, I didn't check the overall syntax, but it has to comply with Verilog rules as well.
I you think, clk2 <= 0 is meaningful for your code, you have to redesign the first always respectively. You can use multiple concurrent assignment inside an always block (the last wins), so it would be possible within the first one.