for your above first post program
this is the tb
usnderstand any doubt plz ask
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb IS
END tb;
ARCHITECTURE behavior OF tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shiftreg
PORT(
din : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
clr : IN std_logic;
pset : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal din : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal clr : std_logic := '0';
signal pset : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shiftreg PORT MAP (
din => din,
clk => clk,
clr => clr,
pset => pset,
q => q
);
-- Clock process definitions
clk_process
rocess
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
pset<='0';
wait for clk_period*10;
clr<='0';
wait for clk_period*10;
pset<='1';
clr<='1';
din<="1100";
wait for clk_period*10;
pset<='1';
clr<='1';
wait for clk_period*10;
pset<='1';
clr<='1';
wait;
end process;
END;
if you dont get this plz dont go to understand and confuse urself