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[SOLVED] [Help on VHDL] FATAL ERROR while loading design

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jianhuachews

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Hi guys, I've just started learning VHDL for a week on my own so i'm still very new to it. I'm doing a practice on implementing a 4-bit parallel-out serial shift register.. My codings can be complied but it shows

" # ** Fatal: (vsim-3347) Port 'din' is not constrained.
# Time: 0 ns Iteration: 0 Instance: /shiftreg File: /EDCP6/proj15/jianhua/vhdl/Lab3_compare.vhd Line: 5
# FATAL ERROR while loading design " when i tried to simulate it. can anyone help me out with this?


***********************************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity shiftreg is port (
din: in std_logic_vector; -- data in
clk: in std_logic; -- Clock
clr: in std_logic; -- Clear
pset: in std_logic; --Preset
q : out std_logic_vector(3 downto 0) -- output Q
);

end;

architecture rtl of shiftreg is
begin

process (clk, clr,pset)
begin
if (pset='0') then
q <= "1111";
elsif (clr='0') then
q <= "0000";
elsif (clk'event and clk = '1') then
q <= din;
end if;

end process;

end rtl;
 

TrickyDicky

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edit : I should really read posts !

You havent given a length to the din port. You either need to instantiate this entity in a testbench with a length, or give a length to the port on the entity.

Eg.

din : in std_logic_vector(7 downto 0);

Without a length, it has no idea how many bits are in the bus.

---------- Post added at 08:41 ---------- Previous post was at 08:39 ----------

and you probably want din to be (3 downto 0).
 

jianhuachews

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Hi dicky! Thanks for replying my thread.

I realised i had left out the input length but for my case, i have a 2-bit input (AND gate) and it does not match with the 4-bit output!
 

TrickyDicky

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then you have to make up the bits somewhere.
 

    V

    points: 2
    Helpful Answer Positive Rating

jianhuachews

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i tried forcing my inputs to a LOW and it works! but then again i realised, i need to be able to switch my input to a HIGH too. Any idea on what should i do?


din1: in std_logic_vector:="0" ;
din2: in std_logic_vector:="0" ;

The codes above does not allow me to force my inputs to a HIGH after simulating it!
 
Last edited:

jianhuachews

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Ok cool i got it solved now. Could anyone tell me what is wrong with my testbench?
Code:
Library IEEE;
Use IEEE.std_logic_1164.all;

Entity shiftregTB is
end;

Architecture rtl of shiftregTB is
	signal A,B,clk,clr,preset: std_logic;
	signal q,q_int :  std_logic_vector(3 downto 0);
	constant clk_period : time := 1 ns;
begin
UUT : entity work.shiftreg port map(A,B,clk,clr,preset,q_int);
     
tb : process
begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
end process tb;

tb2 : process
begin
	preset<='0';
	wait for clk_period*2;
	preset<='1';
	clr<='0';
	wait for clk_period*2;
	preset<='1';
	clr<='1';
	clk<='1';
	A<='1';
	B<='1';
	wait for clk_period*2;
	preset<='1';
	clr<='1';
	clk<='1';
	A<='0';
	wait for clk_period*2;
	preset<='1';
	clr<='1';
	clk<='1';
	B<='0';
	wait for clk_period*2;
	wait;
end process tb2;
	
end;
modelsim shows me this message when tried running it
Error: (vsim-3601) Iteration limit reached at time 0 ns.
 

sanju_

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dont assign clk in this

tb2 : process
begin
preset<='0';
wait for clk_period*2;
preset<='1';
clr<='0';
wait for clk_period*2;
preset<='1';
clr<='1';
clk<='1';
A<='1';
B<='1';
wait for clk_period*2;
preset<='1';
clr<='1';
clk<='1';
A<='0';
wait for clk_period*2;
preset<='1';
clr<='1';
clk<='1';
B<='0';


delete all clk in above code


and
edit this line
UUT : entity work.shiftreg port map(A,B,clk,clr,preset,q_int);
assign to your top level ports to your signals

why signal 'b' is used?
 
Last edited:

jianhuachews

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Hi sanju!

I have tried removing CLK from tb2 : process, but it still generates the same error as before! So instead, i tried another method of writing.

Code:
Library IEEE;
Use IEEE.std_logic_1164.all;

Entity shiftregTB is
end;

Architecture rtl of shiftregTB is
	signal A,B,clk,clr,preset: std_logic;
	signal q,q_int :  std_logic_vector(3 downto 0);

begin
UUT : entity work.shiftreg port map(A,B,clk,clr,preset,q_int);
     
tb : process
	begin
		wait for 50 ns;
		preset <= '0';
		wait for 50 ns;
		preset <='1'; clr<='0';
		wait for 50 ns;
		preset <='1'; clr<='1'; clk<='1'; A<='1'; B<='1';
		wait for 50 ns;
		preset <='1'; clr<='1'; clk<='1'; A<='0';
		wait for 50 ns;
		preset <='1'; clr<='1'; clk<='1'; B<='0';
	end process tb;
	
     q<=q_int;
	
end;
Does it look wrong?
 

sanju_

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for your above first post program


this is the tb
usnderstand any doubt plz ask


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT shiftreg
PORT(
din : IN std_logic_vector(3 downto 0);
clk : IN std_logic;
clr : IN std_logic;
pset : IN std_logic;
q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal din : std_logic_vector(3 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal clr : std_logic := '0';
signal pset : std_logic := '0';
--Outputs
signal q : std_logic_vector(3 downto 0);

-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shiftreg PORT MAP (
din => din,
clk => clk,
clr => clr,
pset => pset,
q => q
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
pset<='0';
wait for clk_period*10;

clr<='0';
wait for clk_period*10;
pset<='1';
clr<='1';
din<="1100";
wait for clk_period*10;
pset<='1';
clr<='1';


wait for clk_period*10;
pset<='1';
clr<='1';
wait;
end process;
END;


if you dont get this plz dont go to understand and confuse urself
 

TrickyDicky

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your clock is set to '1', and never toggles.

For your clock, this is the easiest in a testbench:

signal clk : std_logic := '0';

..
--NOT inside a process
clk <= not clk after 10 ns; --100 MHz clock.
 

FvM

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Code:
constant clk_period : time := 1 ns;
Error: (vsim-3601) Iteration limit reached at time 0 ns.
Your simuator time resolution is set to 1 ns, as the meassage reveals. Unfortunately clk_period/2 refers to zero delay in this case. Change clk_period or time resolution.
 

jianhuachews

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Hey FvM > thanks a lot for the help! I increased the time to 10 ns and it works out totally fine! :)


Hi Tricky thanks for the assistance!
I took your guide line and force the start of waveform to be 0.
Code:
	signal A,B,clk, clr,preset: std_logic := '0';
Also, i didn't know that i need
Code:
clk <= not clk after 10 ns;
to make the clock toggle. Thanks so much it's working now!

---------- Post added at 17:07 ---------- Previous post was at 17:06 ----------

Thanks sanju, it's working now! :)
 

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