help on Synopsys ICC pad cells

[gideonjc]

Hello everyone,

I'm a newbie in IC Design especially in using Synopsys tools
I am working on my design at chip-level using ICC.
Hope someone could help me.
I want to assign and connect my design input and output ports to corresponding pad or IO cells surrounding the core. How do i do it? :-(

Does the layout window (gui) provide a feature to do this? or do i need to code it?

Thanks in advance.

 

[dianin]

Usually the IO pad cells instaintiated at the RTL level. But you can also do it in input netlist . I'm not sure if ICC have feature to do this in GUI.

But If you are adding at the layout stage than formal verification is very complex as those PAD cells were not in RTL but now present in layout. My recommedation is to add the IO pad cells at the RTL level , do synthesise then it would not be an issue at ICC as netlist (input netlist) will have all IO pad cells.