fenglei
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Thanks for your help.Sorry for that I haven't shown the detail while asking the question.I'm really a freshman in this area,and I have tried my best to do it well.But,in my circumstance,nobody has the knowledge.So I ask the question here.Following is the details.The ADC is LTC1867L.Hi,
If youvare not sure whether it can drive 4 pins in parallel, why not use 4 FPGA pins.
I tend to say it will work. But to know it for sure you need to read the datasheets.
ADC: input levels, input currents
FPGA: Otput levels @ which output current.
And how do you think we can know? We don't know which ADC you use, we don't know which FPGA you use, how it is configured.
We don't know speed requirements. We don't have datasheets.
We don't know wiring length and capacitance..
Try it on your own. Tell us what you think ... according the datasheets values.
Klaus
Thanks for your help.Sorry for that I didn't reply in time and I haven't shown the detail while asking the question.I'm really a freshman in this area,and I have tried my best to do it well.But,in my circumstance,nobody has the knowledge.So I ask the question here.Following is the details.The ADC is LTC1867L.
1) because we want to cut down on pins and sample synchronously,so don't use 4 FPGA pins
2) ADC input voltage should be 3.3v,and input current should be 10uA at max.
FPGA output voltage should also be 3.3v,and output current can be set as 4mA,8mA,12mA,16mA,24mA.
3)because I think you are experienced engineer,and maybe you know the problem well;The FPGA is configured by embedded flash.
4)the period between conversion cycles is nearly 78us,and sck is 10Mhz.
5)as for wiring length,the hardware engineer may be casually on this matter.I see the Cin is 2pF in datasheet.
According to the datasheet,4mA should be enough for 10uA*4.If the wiring length is not too long,the time delay on each cs wire should not have too much influence that ADC can't work properly.As for capacitance,I know that it has influnce on the posedge.For current and wiring length,I think the system should be working properly.
Hoping for your reply.I want to know how to analyse the problem like this.
Thanks.Sorry for my late reply. Because we want the 4 ADCs work on the same mode,so tie the 4 cs pin together.Can you explain the following sentence for me.I don't know that much.Your simple diagram is still unclear. Are you planning one common or four separate CS lines? If the SPI bus uses common SCK, MISO and MOSI lines, CS must be separate for each ADC.
SPI needs generally no pull-ups. Layout must observe signal integrity rules depending on the clock speed. Due to fast signal edges of FPGA output signals, there's a risk of ringing SCK edges causing false clocking. Source side series termination may be necessary.
Due to fast signal edges of FPGA output signals, there's a risk of ringing SCK edges causing false clocking. Source side series termination may be necessary.
You are talking about digital inputs? Or analog inputs? Or power supply?2) ADC input voltage should be 3.3v,and input current should be 10uA at max.
Here again I think you rather talk about supply voltage.FPGA output voltage should also be 3.3v,and output current can be set as 4mA,8mA,12mA,16mA,24mA.
Yes, I'm experienced in designing ADC circuits. But my skills in mind reading are really bad ;-). We still don't know which FPGA you want to use. We don't have a datasheet.3)because I think you are experienced engineer,and maybe you know the problem well;The FPGA is configured by embedded flash.
surely is possible. For debugging it may be easier to run the clock with 1MHz.4)the period between conversion cycles is nearly 78us,and sck is 10Mhz.
There is a hardware engineer? He/she surely should be able to determine pin currents and voltages from a datasheet.5)as for wiring length,the hardware engineer may be casually on this matter.I see the Cin is 2pF in datasheet.
As in post#2: I expect no problems. But this is guessing. It depends on the details.According to the datasheet,4mA should be enough for 10uA*4.If the wiring length is not too long,the time delay on each cs wire should not have too much influence that ADC can't work properly.As for capacitance,I know that it has influnce on the posedge.For current and wiring length,I think the system should be working properly.
I see Vol is 0.4V and Voh is (vcco - 0.4v=2.9v)The expectable output voltages at the according pin currents can be found in the FPGA datasheet. They usually are named with Vol and Voh.
What I want is guarantee but not guessing,so,please tell me more about it.I am eager to know more.If you can live with this guessing: all is fine. But no guarantee.
If you need to be sure: You (at first...but we, too) need to know requirement and datasheet details.
Actually,I don't have the schematic either because our engineer hasn't drawn it,but I can draw it by myself.Is it expecting too much if we want a complete schematic that shows the connection of all SPI signals? This would have saved a lot of guesses.
I have no knowledge in this area.Can you tell me more detail about it.?but the ADC SCK input is fast and can react on short edge ringing.
Thanks.Why should the resistor be 47ohm ?Thanks. Question about trace lengths is still pending. I would add series resistor of e.g. 47 ohms to all SPI signals driven by the FPGA to absorb reflected signals. This should be sufficient for medium trace lengths up to e.g. 20 cm.
Hi,I am always here waiting for your instruction.You are talking about digital inputs? Or analog inputs? Or power supply?
Let's say power supply Vdd = 3.3V.
Then the digital input voltage levels are: (datasheet) Vil < 0.45V, Vih > 1.9V
Here again I think you rather talk about supply voltage.
The expectable output voltages at the according pin currents can be found in the FPGA datasheet. They usually are named with Vol and Voh.
Yes, I'm experienced in designing ADC circuits. But my skills in mind reading are really bad ;-). We still don't know which FPGA you want to use. We don't have a datasheet.
Thus it's impossible to answer any question about the FPGA.
surely is possible. For debugging it may be easier to run the clock with 1MHz.
There is a hardware engineer? He/she surely should be able to determine pin currents and voltages from a datasheet.
As in post#2: I expect no problems. But this is guessing. It depends on the details.
If you can live with this guessing: all is fine. But no guarantee.
If you need to be sure: You (at first...but we, too) need to know requirement and datasheet details.
Wiring and PCB layout: --> don't use jumper wires, don't use a breadboard.
Klaus
HiYou are talking about digital inputs? Or analog inputs? Or power supply?
Let's say power supply Vdd = 3.3V.
Then the digital input voltage levels are: (datasheet) Vil < 0.45V, Vih > 1.9V
Here again I think you rather talk about supply voltage.
The expectable output voltages at the according pin currents can be found in the FPGA datasheet. They usually are named with Vol and Voh.
Yes, I'm experienced in designing ADC circuits. But my skills in mind reading are really bad ;-). We still don't know which FPGA you want to use. We don't have a datasheet.
Thus it's impossible to answer any question about the FPGA.
surely is possible. For debugging it may be easier to run the clock with 1MHz.
There is a hardware engineer? He/she surely should be able to determine pin currents and voltages from a datasheet.
As in post#2: I expect no problems. But this is guessing. It depends on the details.
If you can live with this guessing: all is fine. But no guarantee.
If you need to be sure: You (at first...but we, too) need to know requirement and datasheet details.
Wiring and PCB layout: --> don't use jumper wires, don't use a breadboard.
Klaus
oh,maybe,I made a mistake.Nothing to apologize for.
Last time,you asked me to post the datasheet of the FPGA used in the project for guarentee.So,I posted the paper.And,I don't to know if it will work stably and how to analyse.I expect no problems. But this is guessing. It depends on the details.
If you can live with this guessing: all is fine. But no guarantee.
If you need to be sure: You (at first...but we, too) need to know requirement and datasheet details.
Hi,I believe the discussion is missing the point. You can expect that any FPGA with 3.3V CMOS or 3.3V LVTTL IO standard matches the input and output voltage levels of 3.3V SPI peripherals. The point needing attention are PCB layout, trace length and characteristic impedance and possible termination, if required.
Unfortunately you didn't yet gave any information about PCB geometry and expectable connection lengths.
Thanks,what I really need is to know what is important to read in a datasheet.In fact,I haven't thought that you would do it for me.What I really asked is what is inportant in a project and how to analyse.In the past,I only read the timing diagram、pin explanation and configure explanation,and then guess if the whole project will work properly and well.Our engineers don't know for sure either. So I tried to learn how to make the project well.That is the reason why I'm here.Actually,I think you had found that I lack a lot of knowledge even what is essential in a project.Hi,
Yes, FvM, you are correct. Thanks.
@OP:
The datasheet is - in first place - important for you.
In post#5 I wrote: " The expectable output voltages at the according pin currents can be found in the FPGA datasheet. They usually are named with Vol and Voh. "
What I wanted to say: You need to learn to open the datassheet in a PDF reader and do a search on "VOL" or "VOH" or whatever you need to know.
It was not meant that we do this datasheet search for you.
But in case you encounter any problems with (understanding) the datasheet it´s important for us to know what exact device you use and that we have a link to the datasheet to support you.
But we are not here to do your job or do datasheet searches for you. (I´m not upset or angry, saying this) Instead we will help you. We will teach you how to find informations on your own.
Thats at least my goal. To gain knowledge that helps you now - but more important - it should help you for the future.
Klaus
At first: You did not make a mistake.Thanks,what I really need is to know what is important to read in a datasheet.In fact,I haven't thought that you would do it for me.What I really asked is what is inportant in a project and how to analyse.In the past,I only read the timing diagram、pin explanation and configure explanation,and then guess if the whole project will work properly and well.Our engineers don't know for sure either. So I tried to learn how to make the project well.That is the reason why I'm here.Actually,I think you had found that I lack a lot of knowledge even what is essential in a project.
So,I really appreciate the help you have given.
Hi,Hi,
At first: You did not make a mistake.
If there is an engineer as hardware designer, then you even did a part of his job.
I think I wrote how and where to determine the values and I´ve given the typical abbreviations to look for.
If I missed something, or still something is unclear, you are welcome to ask.
Klaus
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