All numbers that calculated are pseudorandom. Even if you feed them with the system time, the resulting sequence is psuedorandom, based on a given distribution. Getting truly random input in a VHDL testbench would be very difficult, as it would hard to hook into a RNG system function (which usually uses something like thermal noise to create a random number.
The whole point about using a known seed in testbenches is for reproducibility. for a given seed, you get a given sequence. Hence if you find a bug, you can easily reproduce the sequence to debug and fix the bug.
I would highly suggest you stick to a given seed (or set of seeds), and just run the test for longer to get more coverage. This way, if theres a bug, you can fix it.
Is there some special reason for using OSVVM? this gives a wealth of number distributions and coverage metrics, but did you know there is a random number generator built into VHDL in the ieee.math_real package? the uniform function takes two positive seed values and gives a pseudo random real between 0 and 1. You can use this to derrive random numbers in any types. I think even part of OSVVM uses this function underneath.
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PS. I dont mean to discourage the use of the OSVVM package. It is very good, but it sounds like you arnt fully aware of testing theory and practice.
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You would only go with a "random" seed if you were running your testbench through regression runs, to try and find any final bugs. For inital debug, you want to stick with a single (or a known set) of seeds.