Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Help on io bank voltage for mixed signaling support

Status
Not open for further replies.

LatticeSemiconductor

Member level 2
Joined
Aug 31, 2013
Messages
45
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
589
Hello, i have trouble on my IO Bank VCCIO requirements. It gives me a conflicting requirement error.

What i am trying to do is using LVDS 2.5 V and LVCMOS 3.3 V signaling standard on the same bank on a Lattice MachXO2
The datasheet says that LVDS25 IO_TYPE is possible as mixed voltage support for 2.5 V differential input, using eighter VCCIO = 2.5V or VCCIO = 3.3V.

I want to use 3.3V VCCIO so i can use other pins on the same bank for LVCMOS 3.3V signaling. I defined VCCIO = 3.3 and IO_TYPE according to pin assignment i chose.

I have possibility to assign reference voltage VREF on that bank for mixed voltage support, so i defined a VREF pin on the bank. This hovever did not solve the problem.

It is mentioned for LVCMOS25 in 3.3 V VCCIO bank that VREF is required to set to certain value. For LVDS it is not mentioned so maybe not required.

Also, i could not assign voltage value to VREF pin, so maybe i need to assign a pin from another bank with VCCIO 2.5 to be used to this one? This does not make sense to me since VCCIOs and VREFs are related to each bank.

Does anyone have experience with mixed voltage banking support and can give me a hint?

thanks


Edit: The device has true LVDS and complementary LVDS (i.e., emulated) io buffer. I did not find any hint on that but assume mixed voltage is supported for both cases.

- - - Updated - - -

I just realized that when i disabled the LVDS25 attributes defined in VHDL, IO_TYPE requirement settings changed back to default LVCMOS25.

As it turns out VREF is not needed, it works now.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top