hi there, i am very new to verilog. I am simply writing a clock generator code
The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?
u cannot generate a clock inside an FPGA.
ur piece of code cannot be synthesised.
did u check ur synthesis rpt.
it wud have given u a warning telling u abt the removal of those unsynthesised signals.
there won't b any problems with the Behavioral simulation.
this is a common misunderstanding in beginners that if you make a clock in simulation you wont need to have a real world clock in your circuit.
in simulation its okay, the clock will be generated. but in a real world implementation you have to have an external clock source connected to some pin of your device.
hi there, i am very new to verilog. I am simply writing a clock generator code
The behavioural simulation seems to be ok with clk_output signal giving a clock, but all i could see from the oscilloscope is a high signal for pin 'clk_output', is there anything i'm missing here?
but even in that case you need a clock "source" from which to divide the clock. so no matter what, you need an external oscillator (its better to use a programmable osc if you need to do experimentation) to drive the logic inside your device.