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# [SOLVED]help on 8-bit count up counter.

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#### karthiga05

##### Member level 2
hi, ive done my code for an 8-bit counter but i do not knw what this portion of the code does. can someone explain it for me? thanks!

begin
ctrrocess(clk, reset)
variable carry : std_logic_vector(7 downto 0) := "00000000";

begin
if reset'event and (reset = '1') then
c_out <= (others => '0');

elsif clk'event and (clk='1') then

c_out(0) <= not c_out(0);
carry(0) := c_out(0);

c_out(1) <= c_out(1) xor carry(0);
carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);
carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);
carry(3) := c_out(3) and carry(2);

c_out(4) <= c_out(4) xor carry(3);
carry(4) := c_out(4) and carry(3);

c_out(5) <= c_out(5) xor carry(4);
carry(5) := c_out(5) and carry(4);

c_out(6) <= c_out(6) xor carry(5);
carry(6) := c_out(6) and carry(5);

c_out(7) <= c_out(7) xor carry(6);
carry(7) := c_out(7) and carry(6);

end if;
end process;

Code:
begin
ctr:process(clk, reset)
This is the opening line for the "counter" process. It is triggered(initiated/called) when CLK or RESET changes states.

Code:
       variable carry : std_logic_vector(7 downto 0) := "00000000";
This is a register that represents the carry bits. In regular arithmetic, if you add
6+7, you get 13. 13 does not fit in the ones column, so you leave the '3' in the resultant's ones position, and you 'carry the 1' to the top of the ten's column. This goes back to elementary school math...

Example, 456+567... (ignore the .'s in front of the numbers below, it's a placeholder for proper character alignment)

. 1 1 <--- carried numbers (ones column, 6+7 = 13 and tens column, 1+5+6 = 12)
. 4 5 6 <--- first number, 456
+ 5 6 7 <--- second number, 567
-------
1 0 2 3

Code:
       begin
if reset'event and (reset = '1') then
c_out <= (others => '0');
Pseudo-code: If RESET changes (reset'event), and RESET is now HIGH ('1'), then the output (c_out) is set to all zeroes.

Code:
           elsif clk'event and (clk='1') then
Pseudo-code: If CLK changes, and CLK is now HIGH ('1'), then perform the addition below...

Code:
                 c_out(0) <= not c_out(0);
carry(0) := c_out(0);

c_out(1) <= c_out(1) xor carry(0);
carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);
carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);
carry(3) := c_out(3) and carry(2);

c_out(4) <= c_out(4) xor carry(3);
carry(4) := c_out(4) and carry(3);

c_out(5) <= c_out(5) xor carry(4);
carry(5) := c_out(5) and carry(4);

c_out(6) <= c_out(6) xor carry(5);
carry(6) := c_out(6) and carry(5);

c_out(7) <= c_out(7) xor carry(6);
carry(7) := c_out(7) and carry(6);
This section simply performs a column-by-column binary addition. It starts at the one's position, and effectively add's 1 (0 to 1, and forces the 0th bit into the next carry column). After that, it looks at the three values in the 1st column, determines if adding them will generate a carry, and sets the 1st column output bit. This ripples along all the way to the 7th column of bits.

It's pretty straightforward if you walk through it with pencil and paper. Try walking through the count-up part of the if statement code from 00000000. Go through it four times to see the carry-forward and ripple through the first few columns.

karthiga05

### karthiga05

Points: 2
c_out(0) <= not c_out(0);
carry(0) := c_out(0);

c_out(1) <= c_out(1) xor carry(0);
carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);
carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);
carry(3) := c_out(3) and carry(2);

c_out(4) <= c_out(4) xor carry(3);
carry(4) := c_out(4) and carry(3);

c_out(5) <= c_out(5) xor carry(4);
carry(5) := c_out(5) and carry(4);

c_out(6) <= c_out(6) xor carry(5);
carry(6) := c_out(6) and carry(5);

c_out(7) <= c_out(7) xor carry(6);
carry(7) := c_out(7) and carry(6);

how does this part of the code do the addition??

Note that each block is a full adder whose outputs are defined by the following equations:
S = a xor b xor c;
C = (a and b) or (b and c) or (a and c);

In your case, the register 'a' is the previous count value. And 'b' is "00000001".
substitute in the equations and you will get the above simplified equations.

karthiga05

### karthiga05

Points: 2
so in this case, c_out(0) <= not c_out(0); means changing c_out to 00000001 right?
thn what would c_out(1)'s value be?? 00000000 or 00000001?

c_out(0) <= not c_out(0);
carry(0) := c_out(0);

c_out(1) <= c_out(1) xor carry(0);
carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);
carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);
carry(3) := c_out(3) and carry(2);

c_out(4) <= c_out(4) xor carry(3);
carry(4) := c_out(4) and carry(3);

c_out(5) <= c_out(5) xor carry(4);
carry(5) := c_out(5) and carry(4);

c_out(6) <= c_out(6) xor carry(5);
carry(6) := c_out(6) and carry(5);

c_out(7) <= c_out(7) xor carry(6);
carry(7) := c_out(7) and carry(6);

Here c_out is a signal and carry is a variable. In vhdl, a signal will be updated with a small delay. So dependent assignments like above will not happen in the same clock cycle. But variable will be updated immediately.

For the first clock cycle:

c_out(0) <='1';
carry(0) := old value of c_out(0) = '1';

c_out(1) <= '1' xor '1' = '0'; --old value of c_out(1) xor with current value of carry(0).
carry(1) := '0' and '0' = '0'; --old value of c_out(1) and with current value of carry(0).

c_out(2) <= '0'; --old value of c_out(2) xor with current value of carry(1).
carry(2) := '0'; --old value of c_out(2) xor with current value of carry(1).

and so on...

In the 2nd clock cycle:

c_out(0) <= not '1' = '0';
carry(0) := '1';

c_out(1) <= '0' xor '1' = '1'; --old value of c_out(1) xor with current value of carry(0).
carry(1) := '0' and '1' = '0'; --old value of c_out(1) and with current value of carry(0).

c_out(2) <= '0'; --old value of c_out(2) xor with current value of carry(1).
carry(2) := '0'; --old value of c_out(2) xor with current value of carry(1).

and so on...

i suggest you write down the values in each clock cycle on a paper. that will help you understand the flow of the program..

karthiga05

### karthiga05

Points: 2
Alright. Thank you! i understand it better now.

c_out is always the old value is it? and carry is always the current value?

Read my last post again and do similar calculations on a paper for first 10 clock cycles. copy paste those calculations here. thats the only way you can understand it.

if you take some effort like that then people will be more happy to answer your questions too.

Read my last post again and do similar calculations on a paper for first 10 clock cycles. copy paste those calculations here. thats the only way you can understand it.

if you take some effort like that then people will be more happy to answer your questions too.

of course i put in effort. i knw hw it works alrdy. thanks

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