#### karthiga05

##### Member level 2

begin

ctrrocess(clk, reset)

variable carry : std_logic_vector(7 downto 0) := "00000000";

begin

if reset'event and (reset = '1') then

c_out <= (others => '0');

elsif clk'event and (clk='1') then

c_out(0) <= not c_out(0);

carry(0) := c_out(0);

c_out(1) <= c_out(1) xor carry(0);

carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);

carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);

carry(3) := c_out(3) and carry(2);

c_out(4) <= c_out(4) xor carry(3);

carry(4) := c_out(4) and carry(3);

c_out(5) <= c_out(5) xor carry(4);

carry(5) := c_out(5) and carry(4);

c_out(6) <= c_out(6) xor carry(5);

carry(6) := c_out(6) and carry(5);

c_out(7) <= c_out(7) xor carry(6);

carry(7) := c_out(7) and carry(6);

end if;

end process;