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[SOLVED] help on 4-bit up counter using hierarchical design

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karthiga05

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hi guys. im currently doing a 4-bit up counter using hierarchical desgin. i have to onclude my half adder and/or fulladder in my design. but im unsure if the ones in red is correct. Also, im not sure abt how to do the port mapping. would really appreciate your help. thanks!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of ha is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;


signal a_in: std_logic_vector(3 downto 0);
signal b_in: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal cout: std_logic_vector(3 downto 0);


begin
counter:process(clk, reset)

begin
if reset'event and (reset = '1') then
c <= (others => '0');
--If RESET changes (reset'event), and RESET is now HIGH '1', then the output (c_out) is set to all zeroes.

elsif clk'event and (clk='1') then
--If CLK changes, and CLK is now HIGH '1', then perform the addition below.

ha1 : ha port map(a => a_in(3), b => b_in(3), sum => c(3));
ha2 : ha port map(a => a_in(2), b => b_in(2), sum => );



end if;
end process;

count <= c;

end behav_counter;

---------- Post added at 11:11 ---------- Previous post was at 10:53 ----------

begin
if reset'event and (reset = '1') then
c <= (others => '0');
--If RESET changes (reset'event), and RESET is now HIGH '1', then the output (c_out) is set to all zeroes.

elsif clk'event and (clk='1') then
--If CLK changes, and CLK is now HIGH '1', then perform the addition below.

ha1 : ha port map(a => a_in, b => b_in, sum => c(3));
ha2 : ha port map(a => c(3), b => b_in, sum => c(2) );
ha3 : ha port map(a => c(2), b => b_in, sum => c(1) );
ha4 : ha port map(a => c(1), b => b_in, sum => c(0) );



end if;
end process;

OR is this correct?
 

sanju_

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hi
VHDL Tutorial - Connecting Blocks -->syntax for port mapping

make your port map inputs/outputs equal to component

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

it containts four ports a,b,sum and c_out

but in this line
ha1 : ha port map(a => a_in, b => b_in, sum => c(3));
it contains only three...a,b,sum one is missing c_out.



lot of expamles on net you may get
VHDL for FPGA Design/4-Bit BCD Counter with Clock Enable - Wikibooks, open books for an open world
VHDL for FPGA Design/4-Bit Binary Counter with Parallel Load - Wikibooks, open books for an open world
VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops
 
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karthiga05

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hi
VHDL Tutorial - Connecting Blocks -->syntax for port mapping

make your port map inputs/outputs equal to component

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

it containts four ports a,b,sum and c_out

but in this line
ha1 : ha port map(a => a_in, b => b_in, sum => c(3));
it contains only three...a,b,sum one is missing c_out.



lot of expamles on net you may get
VHDL for FPGA Design/4-Bit BCD Counter with Clock Enable - Wikibooks, open books for an open world
VHDL for FPGA Design/4-Bit Binary Counter with Parallel Load - Wikibooks, open books for an open world
VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops
ive referred to VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops. What i want is similar to this. bt instead of JK flipflops, i have to use halfadders or fulladders. which is whr im stuck. i dont knw how to compile the halfadder or fulladder to my 4-bit counter using port mapping.

---------- Post added at 16:38 ---------- Previous post was at 16:37 ----------

this is my latest code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of ha is

signal a: std_logic_vector(3 downto 0);
signal b: std_logic_vector(3 downto 0);
signal c: std_logic_vector(3 downto 0);
signal cout: std_logic;


component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

begin

counter:process(clk, reset)
begin
if reset'event and (reset = '1') then
c <= (others => '0');

elsif clk'event and (clk='1') then

ha1:ha port map(a => a(3), b => b(3), sum => c(3), c_out => cout(3));
ha2:ha port map(a => c(3), b => b(2), sum => c(2), c_out => cout(2));
ha3:ha port map(a => c(2), b => b(1), sum => c(1), c_out => cout(1));
ha4:ha port map(a => c(1), b => b(0), sum => c(0), c_out => cout(0));

end if;
end process;

count <= c;

end behav_counter;
 

Kukaz

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Why do you so hard?

It is counter description:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of counter is
SIGNAL count_int : integer RANGE 0 TO 15;

begin
count <= conv_std_logic_vector(coun_int, count'length);

-- reset = asynchonoys !!
process(reset, clk)
begin
if reset = '1' then
count_int <= 0;
elsif clk'event and clk = '1' then
count_int <= count_int + 1;
end if;
end process;
end behav_counter;



if you want to use a counter, write:

component counter
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);

signal clk_1 : std_logic;
signal reset_1 : std_logic;
signal count_out_1 : std_logic_vector (3 downto 0);


-- make item
counter1: counter
port map(
count => count_out_1,
clk => clk_1,
reset => reset_1
);
 
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karthiga05

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Why do you so hard?

It is counter description:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of counter is
SIGNAL count_int : integer RANGE 0 TO 15;

begin
count <= conv_std_logic_vector(coun_int, count'length);

-- reset = asynchonoys !!
process(reset, clk)
begin
if reset = '1' then
count_int <= 0;
elsif clk'event and clk = '1' then
count_int <= count_int + 1;
end if;
end process;
end behav_counter;



if you want to use a counter, write:

component counter
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);

signal clk_1 : std_logic;
signal reset_1 : std_logic;
signal count_out_1 : std_logic_vector (3 downto 0);


-- make item
counter1: counter
port map(
count => count_out_1,
clk => clk_1,
reset => reset_1
);
Im required to ure halfadders or fulladders in my code. i submitted this bt was asked to do it in anthr way.

---------- Post added at 10:35 ---------- Previous post was at 10:31 ----------

port maps are done outside of a process.
thn what do i put under this portion?

if reset'event and (reset = '1') then
c <= (others => '0');

elsif clk'event and (clk='1') then
 

sanju_

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hi...
well you will get error if you use "if" or "process" for port mapping...


tell exectly what you are trying to do or asked to do
(my question is are you trying to port map during positive edge of clock and reset )
 

karthiga05

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yup. i need to do port mapping during positive edge of clock and reset. but im not sure if we are allowed to do port mapping under a process.
this is my latest code :::

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of ha is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;


signal a,b,c1,c2,c3,c4:std_logic;
signal s:std_logic_vector(3 downto 0);

begin

counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
c <= (others => '0');

elsif clk'event and (clk='1') then

--configuration specification
for ha1, ha2, ha3, ha4: ha use entity work.ha(rtl);

ha1:ha port map(a => a, b => b, sum => s(3), c_out => c1);
ha2:ha port map(a => s(3), b => b, sum => s(2), c_out => c2);
ha3:ha port map(a => s(2), b => b, sum => s(1), c_out => c3);
ha4:ha port map(a => s(1), b => b, sum => s(0), c_out => c4);

end if;
end process;

count <= s;

end behav_counter;
 

sanju_

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hi again..
i am not that good in doing structural description's(port mapping)
1: i can suggest that if you understood your older post https://www.edaboard.com/thread216613.html then it apply here also make only four bit and also i have shown syntax VHDL Tutorial - Connecting Blocks for small program....replace this three line by half adder

"c_out(1) <= c_out(1) xor carry(0);
carry(1) := c_out(1) and carry(0);

c_out(2) <= c_out(2) xor carry(1);
carry(2) := c_out(2) and carry(1);

c_out(3) <= c_out(3) xor carry(2);
carry(3) := c_out(3) and carry(2);"

as port map

(or)

2: also i showed you that counter using jk flipflop VHDL coding tips and tricks: 4 bit Synchronous UP counter(with reset) using JK flip-flops check their in jk flip flop they used rising edge of clock and reset and they port mapped to counter program also they have showen that their is no process or if statment is used implemented counter...

hope this helps.



--configuration specification
for ha1, ha2, ha3, ha4: ha use entity work.ha(rtl); this line replace to
f--configuration specification
for all: ha use entity work.ha(rtl); put it near signals(before begin )
 

karthiga05

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thanks but im required to use port mapping. i understand the other codes. but my supervisor wants me to use portmapping. ive tried what u asked me to do. but it still shows an error.
 

TrickyDicky

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Thats fine, just dont put the port mapping inside a process, because it's illegal code. Only signals go inside a process.
 

Kukaz

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entity counter is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter;

architecture behav_counter of cointer is

component fulladdar port (
a: in std_logic;
b: in std_logic;
c_in: std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

signal one : std_logic_vector (3 downto 0):= "0001";
signal summ : std_logic_vector (3 downto 0);
signal c0 : std_logic;
signal c1 : std_logic;
signal c2 : std_logic;

signal s0 : std_logic;
signal s1 : std_logic;
signal s2 : std_logic;
signal s3 : std_logic;

begin

count <= summ;

process(reset, clk)
begin
if reset = '1' then
summ <= (others => '0');
elsif clk'event and clk ='1' then
summ(0) <= s0;
summ(1) <= s1;
summ(2) <= s2;
summ(3) <= s3;
end if;

fa0: fulladder
port map(
a => one(0),
b => summ(0),
c_in => '0',
sum => s0,
c_out => c0
);

fa1: fulladder
port map(
a => one(1),
b => summ(1),
c_in => c0,
sum => s1,
c_out => c1
);

fa2: fulladder
port map(
a => one(2),
b => summ(2),
c_in => c1,
sum => s2,
c_out => c2
);

fa3: fulladder
port map(
a => one(3),
b => summ(3),
c_in => c2,
sum => s3,
c_out => null
);

end behav_counter;
 

karthiga05

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im required to use 1 halfadder and 3 fulladders.
 

sanju_

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hi in above code you can make one half adder
"fa0: fulladder
port map(
a => one(0),
b => summ(0),
c_in => '0',
sum => s0,
c_out => c0
);"---------------------------------->if you remove "c_in" its half adder so you will get one half and three full adders

hope it work's
 

karthiga05

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my problem now is actually the clk'event portion.
 

karthiga05

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pls help. im still stuck at the clk'event portion. :(

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter4 is
port(count:eek:ut std_logic_vector(3 downto 0);
clk:in std_logic;
reset:in std_logic);
end counter4;

architecture behav_counter4 of counter4 is

component ha port (a: in std_logic;
b: in std_logic;
sum: out std_logic;
c_out: out std_logic);
end component;

component fa port (a, b, cin : in std_logic;
sum, c_out : out std_logic);
end component;

signal ain,s,c:std_logic_vector(3 downto 0) :="0000";
signal bin:std_logic_vector(3 downto 0):="0001";

--configuration specification
for all:ha use entity work.ha(rtl);
for all:fa use entity work.fa(fa_behav);

begin
u1:ha port map(a => ain(0), b => bin(0), sum => s(0), c_out => c(0));
u2:fa port map(a => ain(1), b => bin(1), sum => s(1), cin => c(0), c_out => c(1));
u3:fa port map(a => ain(2), b => bin(2), sum => s(2), cin => c(1), c_out => c(2));
u4:fa port map(a => ain(3), b => bin(3), sum => s(3), cin => c(2), c_out => c(3));


counter:process(clk, reset) --process(sensitivity list)
begin
if reset'event and (reset = '1') then
s <= (others => '0');

elsif clk'event and (clk='1') then
ain <= c xor ain;
s <= ain xor bin;
c <= s and c;
ain <= c xor ain;

end if;
end process;

count <= s;

end behav_counter4;
 

sanju_

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hi
"if reset'event and (reset = '1') then" this you cant use.
use "if reset= '1' then"
 

karthiga05

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hi
"if reset'event and (reset = '1') then" this you cant use.
use "if reset= '1' then"
really?
bt my supervisor told me tht, tht part is fine. its only my clk'event.

elsif clk'event and (clk='1') then
ain <= c xor ain;
s <= ain xor bin;
c <= s and c;
ain <= c xor ain;

he wants me to create a loop here. so tht it'll add.
 

karthiga05

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Its ok. i figured it out. thanks! will get back here if i face a prob again. lol
 

VHDL92

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Need the completed code for this. Beggin!!!
 

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