#### karthiga05

##### Member level 2

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

port(countut std_logic_vector(3 downto 0);

clk:in std_logic;

reset:in std_logic);

end counter;

architecture behav_counter of ha is

component ha port (a: in std_logic;

b: in std_logic;

sum: out std_logic;

c_out: out std_logic);

end component;

**signal a_in: std_logic_vector(3 downto 0);**

signal b_in: std_logic_vector(3 downto 0);

signal c: std_logic_vector(3 downto 0);

signal cout: std_logic_vector(3 downto 0);

signal b_in: std_logic_vector(3 downto 0);

signal c: std_logic_vector(3 downto 0);

signal cout: std_logic_vector(3 downto 0);

begin

counterrocess(clk, reset)

begin

if reset'event and (reset = '1') then

c <= (others => '0');

--If RESET changes (reset'event), and RESET is now HIGH '1', then the output (c_out) is set to all zeroes.

elsif clk'event and (clk='1') then

--If CLK changes, and CLK is now HIGH '1', then perform the addition below.

ha1 : ha port map(a => a_in(3), b => b_in(3), sum => c(3));

ha2 : ha port map(a => a_in(2), b => b_in(2), sum => );

ha1 : ha port map(a => a_in(3), b => b_in(3), sum => c(3));

ha2 : ha port map(a => a_in(2), b => b_in(2), sum => );

end if;

end process;

count <= c;

end behav_counter;

---------- Post added at 11:11 ---------- Previous post was at 10:53 ----------

begin

if reset'event and (reset = '1') then

c <= (others => '0');

--If RESET changes (reset'event), and RESET is now HIGH '1', then the output (c_out) is set to all zeroes.

elsif clk'event and (clk='1') then

--If CLK changes, and CLK is now HIGH '1', then perform the addition below.

ha1 : ha port map(a => a_in, b => b_in, sum => c(3));

ha2 : ha port map(a => c(3), b => b_in, sum => c(2) );

ha3 : ha port map(a => c(2), b => b_in, sum => c(1) );

ha4 : ha port map(a => c(1), b => b_in, sum => c(0) );

ha1 : ha port map(a => a_in, b => b_in, sum => c(3));

ha2 : ha port map(a => c(3), b => b_in, sum => c(2) );

ha3 : ha port map(a => c(2), b => b_in, sum => c(1) );

ha4 : ha port map(a => c(1), b => b_in, sum => c(0) );

end if;

end process;

OR is this correct?