billjoy
Member level 1

setenv in verilog makefile
Q1:
In NC
if ncvhdl
ncverilog
is ok
but
ncelab with error **broken link removed**
Here is my run procesure
/==========
ncvhdl -work work ./fa.vhd ==> OK
ncvlog -work work ./adder4.v ==> OK
ncvhdl -work work ./testfixture.vhd ==> OK
ncelab -work work work.cfg_testadd4:configuration ==> not OK
--> message
ncelab:*E,MULVHD
ossible bindings for instance of entity 'fa' in
`work.add4:module' are :
VITAL_MEMORY.FA :A
WORk.FA:A
ncelab : *E,CUVMUR:instance for module/UDP 'fa' in unsolved
in 'work.add4:module'.
//=============
what does this mean??
what elab is error??
Q2. In this case , I want to use ncsim generate *.fsdb
Is any master guy can tell me how to do this?
Q1:
In NC
if ncvhdl
ncverilog
is ok
but
ncelab with error **broken link removed**
Here is my run procesure
/==========
ncvhdl -work work ./fa.vhd ==> OK
ncvlog -work work ./adder4.v ==> OK
ncvhdl -work work ./testfixture.vhd ==> OK
ncelab -work work work.cfg_testadd4:configuration ==> not OK
--> message
ncelab:*E,MULVHD
`work.add4:module' are :
VITAL_MEMORY.FA :A
WORk.FA:A
ncelab : *E,CUVMUR:instance for module/UDP 'fa' in unsolved
in 'work.add4:module'.
//=============
what does this mean??
what elab is error??
Q2. In this case , I want to use ncsim generate *.fsdb
Is any master guy can tell me how to do this?