TuAtAu
Advanced Member level 4
Hi guys, this is the problem that I face.
I declare a std_logic_vector
e.g.
entity:
PORT1_IN : in std_logic_vector(31 downto 0);
-- means I got 32 bits on a port
--then
--i wish to choose the number of bits instead of array, how do I do it.
e.g.
variable COUNTER : integer range 0 to 16;
COUNTER := COUNTER +1;
PORT1_IN(COUNTER) <= '1'; -- <-- If i do like that, it assume that I am choosing the Array!! not BITS! so i got error on Index value(s) does not match array range, simulation mismatch when SYNTHESIS. SOS, I am run out of ideas and I search google already.. no solution yet.
:-(
---------- Post added at 17:28 ---------- Previous post was at 17:13 ----------
For edition
I want to check in conditional :
If (PORT1_IN(COUNTER) = '1') then --This is error because it treat my PORT1_IN is an array and it is choosing the "COUNTER"th elements.. But what I want is vector
So how do I edit to make it to choose VECTOR instead of ARRAY?
I declare a std_logic_vector
e.g.
entity:
PORT1_IN : in std_logic_vector(31 downto 0);
-- means I got 32 bits on a port
--then
--i wish to choose the number of bits instead of array, how do I do it.
e.g.
variable COUNTER : integer range 0 to 16;
COUNTER := COUNTER +1;
PORT1_IN(COUNTER) <= '1'; -- <-- If i do like that, it assume that I am choosing the Array!! not BITS! so i got error on Index value(s) does not match array range, simulation mismatch when SYNTHESIS. SOS, I am run out of ideas and I search google already.. no solution yet.
:-(
---------- Post added at 17:28 ---------- Previous post was at 17:13 ----------
For edition
I want to check in conditional :
If (PORT1_IN(COUNTER) = '1') then --This is error because it treat my PORT1_IN is an array and it is choosing the "COUNTER"th elements.. But what I want is vector
So how do I edit to make it to choose VECTOR instead of ARRAY?