[SOLVED] [HELP] Number of Bits vs. Number of Array [VHDL]

[TuAtAu]

Hi guys, this is the problem that I face.

I declare a std_logic_vector
e.g.

entity:

PORT1_IN : in std_logic_vector(31 downto 0);

-- means I got 32 bits on a port
--then
--i wish to choose the number of bits instead of array, how do I do it.

e.g.

variable COUNTER : integer range 0 to 16;

COUNTER := COUNTER +1;

PORT1_IN(COUNTER) <= '1'; -- <-- If i do like that, it assume that I am choosing the Array!! not BITS! so i got error on Index value(s) does not match array range, simulation mismatch when SYNTHESIS. SOS, I am run out of ideas and I search google already.. no solution yet.
:-(

---------- Post added at 17:28 ---------- Previous post was at 17:13 ----------

For edition

I want to check in conditional :
If (PORT1_IN(COUNTER) = '1') then --This is error because it treat my PORT1_IN is an array and it is choosing the "COUNTER"th elements.. But what I want is vector

So how do I edit to make it to choose VECTOR instead of ARRAY?

 

[permute]

I'm assuming the assignment to port1_in is the mistake, as you are attempting to drive a value onto the input port. While VHDL does support multiple drivers on the same signal, it generally is a mistake.

As for your error, I'm not sure. possibly it is an issue with you synthesizer.

edit -- the "error" probably should have been a warning, as sim-mismatches often are. The issue probably is that the variable infers a 5b value that, in implementation has a range of 0 to 31. This is because you have 17 values that the integer can take -- 0 to 16.

 

[TuAtAu]

YES! permute you are right,
after i change my COUNTER to 32 -- 0 to 31
it solve the warning, BUT
my COUNTER is also use on another port which only has
R_IN: out std_logic_vector (15 downto 0);

So if I solve the PORT1_IN error by change to int32, the R_IN(COUNTER) <= '1'; mismatch again...

any win-win situation? to match both ?

---------- Post added at 18:11 ---------- Previous post was at 17:57 ----------

SOLVED!!
Thanks permute~! your reply really put me in the right rail in troubleshooting.


COUNTER : integer range 0 to 31

PORT1_IN(COUNTER) <= '1';
R_IN(conv_integer(conv_unsigned(COUNTER,4)))) <= '1'

working fine!

 

[permute]

i'm pretty sure the synthesizer also accepts R_In(counter mod 16)

likewise, for sim, you probably need to do counter := (counter +1) mod 32;