Help needed.. parallel to serial converter in VHDL

Hi, can anybody please give me a vhdl code to convert 8 bit parallel data into serial data along with its testbench, if you have it? Please. Its urgent.

Thanks,
Sharada

Help needed.. parallel to serial converter

here is a code, this will only work when the input en is changed along with the posedge of clock.

//------------- RTL --------------------//

module p2s(clk,rst,en,din,dout);

input clk,rst,en;
input [7:0] din;
output dout;
reg dout;

wire pos_edge_detect;
reg flag,enable;
reg [7:0] temp;

assign pos_edge_detect = (en && ~temp);

always@(posedge clk or negedge rst)
if(!rst)
temp <= 8'b0;
else if(en)
temp <= din;
else if(enable)
temp <= {1'b0,temp[7:1]};
else
temp <= temp;

always@(posedge clk or negedge rst)
if(!rst)
flag <= 1'b0;
else
flag <= en;

always@(posedge clk or negedge rst)
if(!rst)
enable <= 1'b0;
else if(pos_edge_detect && temp != 8'b0)
enable <= 1'b1;
else if(temp==8'b0)
enable <= 1'b0;

always@(posedge clk or negedge rst)
if(!rst)
dout <= 1'b0;
else if(enable)
dout <= temp[0];

endmodule


// --------------- Test bench --------------- //


`include "./rtl.v"
module tb_p2s();

reg clk,rst,en;
reg [7:0] din;
wire dout;

p2s p1(.clk(clk),
.rst(rst),
.din(din),
.en(en),
.dout(dout)
);

initial
begin
$recordfile("p2s.trn");
$recordvars();
end

initial
begin
clk = 1'b1;
rst = 1'b0;
en = 1'b0;
#25 rst = 1'b1;
#25 en=1'b1;
din = 8'h45;
#10 en = 1'b0;
#100 $finish();
end

always
clk = #5 ~clk;

endmodule

Re: Help needed.. parallel to serial converter

Thanks a lot for the help. But I want the vhdl code. Can u please help me.

i don't have any vhdl simulator with me, so, i've tried my level best to come up with vhdl rtl. let me know if it compiles alrite.

-- RTL --

library ieee;
use ieee.std_logic_1164.all;


entity rtl is
port (clk,en, rst : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic));


architecture a of rtl is
signal temp : std_logic_vector(7 downto 0);
signal pos_edge_detect : std_logic;
signal flag,enable : std_logic;

begin
process (clk,rst)
begin
if(rst='0')then
temp <= (others=>'0');
elsif(clk='1' and clk'event)then
if(en='1')then
temp <= din;
elsif(enable='1')then
temp <= '0' & temp(7 downto 1);
else
temp <= temp;
end if;
end if;
end process;

process (clk,rst)
begin
if(rst='0')then
flag<='0';
elsif(clk='1' and clk'event)then
flag<=en;
end if;
end process;

process(clk,rst)
begin
if(rst='0')then
enable<='0';
elsif(clk='1' and clk'event)then
if(pos_edge_detect and temp /= "00000000")then
enable <= '1';
elsif(temp="00000000")then
enable <= '0';
end if;
end if;
end process;

process(clk,rst)
begin
if(rst='0')then
dout <= '0';
elsif(clk='1' and clk'event)then
if(enable='1')then
dout <= temp(0);
end if;
end if;
end process;

end architecture a;

Added after 17 minutes:

-- Test bench
-- Not sure if this will work or not

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_rtl is
end entity;

architecture tb of tb_rtl is
component rtl
port( clk, en, rst : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic
);
end component;
begin
u_rtl : rtl port map (clk=>clk,
en=>en,
rst=>rst,
din=>din,
dout=>dout);

process
begin
clk <='1';
wait for 5 ns;
clk <= '0';
wait for 5 ns;
end process;

process
begin
rst <= '1';
wait for 30 ns;
rst <= '0';
en <= '1';
din <= "10101010";
wait for 10 ns;
en <= '0';
end process;
end architecture tb;