i see.. now its work correctly as i wan. thx
using this name associate is much more easy for beginner..
can help me create a serial-parallel and parallel-serial register using this DFF?
a block diagram maybe so i can work on the VHDL code.
Added after 1 hours 3 minutes:
this is for my serial - parallel register
VHDL code
library ieee;
use ieee.std_logic_1164.all;
entity regsp is
port ( SI :IN std_logic_vector (3 downto 0);
Load,clk :IN std_logic;
P :OUT std_logic_vector (3 downto 0));
end regsp;
architecture logic of regsp is
signal s0 : std_logic;
signal s1 : std_logic;
signal s2 : std_logic;
component dfflop
port (D,clock :IN std_logic;
Q :OUT std_logic);
end component;
begin
stage0 : dfflop port map (D =>SI,clock=>clk,Q=> s0);
stage1 : dfflop port map (D =>s0,clock=>clk,Q=> s1);
stage2 : dfflop port map (D =>s1,clock=>clk,Q=> s2);
stage3 : dfflop port map (D =>s2,clock=>clk,Q=> P(3));
P(0)<=s0;
P(1)<=s1;
P(2)<=s2;
end logic;
got some error for my serial input logic type. Suppose for serial input it is like 1100 then for declaration it should be SI :IN std_logic_vector (3 downto 0)??