Draw fsm and write VHDL code for a system which has is single bit input x and two single bit outputs Y and Z. output of system is asserted logic 1 to Y and Z when system detects in input stream of serial bits 0111 or 0101 respectively
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Draw fsm and write VHDL code for a system which has is single bit input x and two single bit outputs Y and Z. output of system is asserted logic 1 to Y and Z when system detects in input stream of serial bits 0111 or 0101 respectively