Thanks so much for your replay. Is there anything I can do in the schematic simulation in Cadence to improve the Q factor?
I tried to increase the width of spirals which improves the output power a little bit but that limits the max inductance a spiral inductor can represent within 300umX300um size, which means I have to use two inductors in series instead of one.
Do you know what's general measured drain efficiency and simulation results using processed spiral inductors in single-ended Class E power amplifier? As far as I know, it is above 80% in ideal cases in simulation. For measured results, it seems the most of Class E PA seldom achieve drain efficiency above 70% as far as to the papers I have read. What do you know about it? I am trying to find the potential/max drain efficiency for a single ended Class E PA can achieve in measured results when it is integrated in a chip.
Do you think differential topology for Class E PA instead of single-ended one can boost it's output power and drain efficiency? Or any other topology?
By the way, do you know if there is any other important/necessary methods of evaluating Class E PA performance besides Drain Efficiency, Power Added Efficiency and Output Power?
Thanks again for your help.