sharethewell
Member level 5
I am designing a single ended Class E power amplifier with a very basic topology commonly seen in papers. The Vdd is 1.2 V and operation frequency is 433 MHz. I am using CMOS as transistors in the design (0.13um process).
When I simulated my circuit with all processed components except using ideal inductors in stead of processed spiral inductors, my PA can achieve more than 80% of drain efficiency and output power can achieve more than 32mW. However when I replaced the ideal inductors with the processed spiral ones, there is a huge power loss in the circuit which makes drain efficiency drop to 55%-60% and Pout drop to 16 mW.
I have been retuning the circuit for a long time in Cadence Spectre, and the drain efficiency and Pout just don't go up at all without sacrificing the correct output voltage and current waveforms. What should I do? I really need help and suggestions on things I can try. Thank you.
When I simulated my circuit with all processed components except using ideal inductors in stead of processed spiral inductors, my PA can achieve more than 80% of drain efficiency and output power can achieve more than 32mW. However when I replaced the ideal inductors with the processed spiral ones, there is a huge power loss in the circuit which makes drain efficiency drop to 55%-60% and Pout drop to 16 mW.
I have been retuning the circuit for a long time in Cadence Spectre, and the drain efficiency and Pout just don't go up at all without sacrificing the correct output voltage and current waveforms. What should I do? I really need help and suggestions on things I can try. Thank you.