Help needed in power loss in RF Class E power amplifier

[sharethewell]

I am designing a single ended Class E power amplifier with a very basic topology commonly seen in papers. The Vdd is 1.2 V and operation frequency is 433 MHz. I am using CMOS as transistors in the design (0.13um process).

When I simulated my circuit with all processed components except using ideal inductors in stead of processed spiral inductors, my PA can achieve more than 80% of drain efficiency and output power can achieve more than 32mW. However when I replaced the ideal inductors with the processed spiral ones, there is a huge power loss in the circuit which makes drain efficiency drop to 55%-60% and Pout drop to 16 mW.

I have been retuning the circuit for a long time in Cadence Spectre, and the drain efficiency and Pout just don't go up at all without sacrificing the correct output voltage and current waveforms. What should I do? I really need help and suggestions on things I can try. Thank you.

 

[BigBoss]

Class-E Power Amplifiers are very sensitive to component parameters ( temperature,process variations,tolerances etc.). Therefore it's very normal to loose 3dB power with a realistice coil.But there is one more thing to do is that increase the Q factor of the coil by laying down a polysilicon pattern under the coil and if it's possible use 2 parallel metalic layers to construct your coil.

 

[sharethewell]

Thanks so much for your replay. Is there anything I can do in the schematic simulation in Cadence to improve the Q factor?

I tried to increase the width of spirals which improves the output power a little bit but that limits the max inductance a spiral inductor can represent within 300umX300um size, which means I have to use two inductors in series instead of one.

Do you know what's general measured drain efficiency and simulation results using processed spiral inductors in single-ended Class E power amplifier? As far as I know, it is above 80% in ideal cases in simulation. For measured results, it seems the most of Class E PA seldom achieve drain efficiency above 70% as far as to the papers I have read. What do you know about it? I am trying to find the potential/max drain efficiency for a single ended Class E PA can achieve in measured results when it is integrated in a chip.

Do you think differential topology for Class E PA instead of single-ended one can boost it's output power and drain efficiency? Or any other topology?

By the way, do you know if there is any other important/necessary methods of evaluating Class E PA performance besides Drain Efficiency, Power Added Efficiency and Output Power?

Thanks again for your help.

 

[tc1220]

Normally, drain efficiency 80% is a quite good result.

Using differentical topology can double the output power.

Actually PAE and output power are two important parameters for PAs.

The above is my understandy for PA

 

[sharethewell]

The output signal of the PA has distortion to a certain degree. The the minus peak of the output voltage (sinusoid) is less than the positive peak when you compare both in absolute value. So after retuning the the circuit to minimize the distortion as much as possible and adding pad circuits, the Drain Efficiency drops to 30% finally.