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Help Needed for VHDL expression Error

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preet

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signal cc_c : std_logic;

variable right_operand : word;
variable tmp_result : unsigned(word'length downto 0);

tmp_result := ('0' & GPR_r1) + ('0' & right_operand)+ resize(unsigned'('0' & cc_c), word'length + 1);

ERROR:HDLParsers:827: The above expression can not be qualified by type unsigned
ERROR:HDLParsers:3324: IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value.

Please guide me for the above error

Warm Regards
 

preet

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subtype word is unsigned(31 downto 0);
 

sanju_

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hi..
in resize(unsigned'('0' & cc_c)
cc_c is std_logic
tmp_result is unsigned
weather it matches both types??
well its my question.
 

TrickyDicky

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sanju, that is not the problem. The unisnged' is a qualifier to tell the compiler it's an unsiged.

Preet - the 'length attribute is not defined for types. use right_operand'length instead.
 

childs

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Am more interested on 2nd warning:
ERROR:HDLParsers:3324: IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value

Can you show the part you instantiate & declare "resize"? Thanks
 

preet

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dear childs
both the error are pointing to same statement
 

FvM

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Just an observation, the code compiles without errors in Altera Quartus, with IEEE.numeric_std.all imported for resize().
 

preet

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Just an observation, the code compiles without errors in Altera Quartus, with IEEE.numeric_std.all imported for resize().


Dear FvM,

Will get back to you after synsthesizing thru Quartus

Thanks and Regards
Preet
 

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