Mar 21, 2010 #1 S shivams Junior Member level 1 Joined Feb 13, 2010 Messages 15 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location pune Activity points 1,361 FPGA basics FPGA is volatile...so how its data is retrieved once the power is turned off?? pls help...am a beginner not clear with the basics.. thanks
FPGA basics FPGA is volatile...so how its data is retrieved once the power is turned off?? pls help...am a beginner not clear with the basics.. thanks
Mar 21, 2010 #2 F farhada Advanced Member level 2 Joined Oct 1, 2004 Messages 587 Helped 84 Reputation 168 Reaction score 30 Trophy points 1,308 Location Nice, France Activity points 5,025 All SRAM based FPGAs download their date from a FLASH based EEPROM at start up, via JTAG, SPI or parallel interface. You have some basic info at: https://www.fpga4fun.com/FPGAinfo7.html
All SRAM based FPGAs download their date from a FLASH based EEPROM at start up, via JTAG, SPI or parallel interface. You have some basic info at: https://www.fpga4fun.com/FPGAinfo7.html
Mar 24, 2010 #3 S sudhirkv Advanced Member level 4 Joined Dec 13, 2005 Messages 106 Helped 8 Reputation 16 Reaction score 1 Trophy points 1,298 Location Chennai, India Activity points 1,992 FPGA's r volatile. But FPGA's have either an on Chip PROM or external PROM to have the configuration file. Once its powered up FPGA loads the configuration file from the PROM and starts working once configuration is done.
FPGA's r volatile. But FPGA's have either an on Chip PROM or external PROM to have the configuration file. Once its powered up FPGA loads the configuration file from the PROM and starts working once configuration is done.