Hi ,
Actually, SDC is a standard design constrainint file. So if you are defining by PT command .. and you are sure that you are defining all the required parameters then there is no need of that.
Now do the following things and see the result... (as you are saying that you are getting 'no constrained paths found'.)
check the output of following commands-
check_timing
report_analysis_coverage
report_constraint
report_exception -ignore >> will tell you why a particular constraint is ignoring.
timing_report_unconstraint_paths
what I am trying to communicate here is .. the reaosn of this messgae may be because of following reason and you have to find out that properly.
1) clock is not defined properly.
2) you have defined any constrainint on all the path in such a way that PT is ignorining all the paths. Like false path or ignore path or ignore any timing arc and so on.
let me know if this will help you. I will suggest you that if youo can provide the snapshot of these commands.. that will help me to figure out the problem.
set input_delay -rise 1.0 { all the inputs }
if the clock is defined exactly like this, you actually don't have a clock since a clock pin is not specified.create_clock -name CLK -period 10.0
Hi,
One more thing if you can copy paste the output of report_analysis_coverage -status_details {untested}.. then it will be good.. I wana see what's the string in the PIN columb. Then I can provide you more accurate command to do some testing.
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