Help needed about PrimeTime

[dhaval4987]

I have been using nanotime for some time and was able to export the critical path as a spice netlist.

I want the critical path in verilog. I dont think it is possible in Nanotime. But someone just told me that it is possible in PrimeTime.

I tried to follow the exact same steps as in Nanotime. But after linking design, I dont know how to follow. I just want similar command of 'trace_paths' (Which calculated and lists all path with delay in descending order). Also I want verilog description of just the path with maximum delay.

Can anyone help?

 

[hanif]

Hi,

check these links

ptsi

JCUI Marvell: si_xtalk_double_switching_mode

 

[dhaval4987]

Thanks Hanif,

But this focuses on Cross Talk analysis. I just want to know about normal analysis and especially list of paths with delays. Couldnt find about it in that!

Also how can we export one specific path as synthesized verilog?

Is it even possible in PT?

 

[dhaval4987]

Dear All,

Here are the steps that I follow but still fail in doing the timing analysis. Please show me where am I going wrong. It is a pure combinational circuit and so I do not have much design constraint. I just need a list of critical paths and also want a specific path to be exported as a verilog netlist.

*****************
set search_path {.}

set link_path {*}

read_db lib_typical.db

read_verilog circuit.v

link_design TOP

(It then shows that design successfully linked)

create_clock -name CLK -period 10.0

set input_delay -rise 1.0 { all the inputs }

(And same for fall delay and additional delay)

set output_delay 0.0 { all the outputs }

report_timing

***************************

However it shows no paths, and says 'no constrained paths found'.

Please help. I am stuck here.

 

[birdy123]

Hi,

What about read_parasitic or read_SDC??

 

[dhaval4987]

Is that a required step? I just want to do STA for a pre spice- i.e. without parasitics. I was able to perform STA in Nanotime without parasitic info.

If that is the required info, then where do I get sdc file? And again, is that required step?

 

[birdy123]

Hi ,

Actually, SDC is a standard design constrainint file. So if you are defining by PT command .. and you are sure that you are defining all the required parameters then there is no need of that.

Now do the following things and see the result... (as you are saying that you are getting 'no constrained paths found'.)

check the output of following commands-
check_timing
report_analysis_coverage
report_constraint
report_exception -ignore >> will tell you why a particular constraint is ignoring.
timing_report_unconstraint_paths

what I am trying to communicate here is .. the reaosn of this messgae may be because of following reason and you have to find out that properly.
1) clock is not defined properly.
2) you have defined any constrainint on all the path in such a way that PT is ignorining all the paths. Like false path or ignore path or ignore any timing arc and so on.


let me know if this will help you. I will suggest you that if youo can provide the snapshot of these commands.. that will help me to figure out the problem.

 

[dhaval4987]

Hi ,

Actually, SDC is a standard design constrainint file. So if you are defining by PT command .. and you are sure that you are defining all the required parameters then there is no need of that.

Now do the following things and see the result... (as you are saying that you are getting 'no constrained paths found'.)

check the output of following commands-
check_timing
report_analysis_coverage
report_constraint
report_exception -ignore >> will tell you why a particular constraint is ignoring.
timing_report_unconstraint_paths

what I am trying to communicate here is .. the reaosn of this messgae may be because of following reason and you have to find out that properly.
1) clock is not defined properly.
2) you have defined any constrainint on all the path in such a way that PT is ignorining all the paths. Like false path or ignore path or ignore any timing arc and so on.


let me know if this will help you. I will suggest you that if youo can provide the snapshot of these commands.. that will help me to figure out the problem.

Here are the results:
*************
check_timing

Information: Checking 'no_input_delay'
Information: Checking 'no_driving_cells'
Information: Checking 'unconstrained_endpoints'
Information: Checking 'unexpandable_clocks'
Information: Checking 'latch_fanout'
Information: Checking 'no_clock'
Information: Checking 'partial_input_delay'
Information: Checking 'generic'
Information: Checking 'loops'
Information: Checking 'generated_clocks'
Information: Checking 'pulse_clock_non_pulse_clock_merge'
Information: Checking 'pll_configuration'

1.


report_analysis_coverage
- Says there are total 22 points out of which 0 meets set up and hold requirements, 0 violates setup and hold requirements and 22(all) are untested.

report_constraint

-This design has no constraints

report_exceptions -ignored

1.

timing_report_unconstraint_paths
- says

Error: unknown command.

So in short, I got to know that it is not testing any paths. but do not understand how do i make it work!?

 

[lostinxlation]

set input_delay -rise 1.0 { all the inputs }

Isn't it supposed to be set_input_delay ?
And you didn't specify the associated clock for input/output constraints.

 

[dhaval4987]

@lostinxlation,

yes it is the way you suggested. I might have missed it out in briefing here. I do mention clock name and also the command is without error.

Still I am stuck as mentioned in my previous post.

Let me know,

Thanks.

 

[lostinxlation]

Post the actual constraint file and STA scripts.

create_clock -name CLK -period 10.0

if the clock is defined exactly like this, you actually don't have a clock since a clock pin is not specified.

Let's see the entire script you have.

EDIT; oops, sorry. I missed that you said the logic is combinatorial. Your clock definition should be fine.

 

[birdy123]

Hi,

nice to see that you have done this.. now let see first this..

report_analysis_coverage
- Says there are total 22 points out of which 0 meets set up and hold requirements, 0 violates setup and hold requirements and 22(all) are untested.

so the untested means-- either those paths are disables or false path or something like this.

so do one thing .. now run the following command...
report_analysis_coverage -status_details {untested}

it will give you a detailed report with respect to all the untested path with there proper reason. Like reason is no_clock .. etc. the reason of this may be any othe the following (with proper detail)..

• constant_disabled: Paths to this check are disabled because of case analysis or a logic constant propagated through the design (for example, caused by a signal tied high or low).

• mode_disabled: A timing constraint is disabled because it requires a mode to be selected in mode analysis, and that mode is not selected.

• user_disabled: The timing check is explicitly disabled by the user.

• no_paths: The timing check had no paths found to it and as a result there were no arrival times.

• false_paths: All paths were false to a constrained pin.

• no_endpoint_clock: The timing check has no destination clock signal to latch the data.

• no_startpoint_clock: The timing check has no clock that launches the data at a startpoint latch.

• no_constrained_clock: There is no constrained clock for skew or clock separation checks.

• no_ref_clock: There is no reference clock for skew or clock separation checks.

• no_clock: A minimum pulse width or period width check has no clock.

• unknown: The reason is not listed above.

This will provide a reason of not testing... let me know the result .. may be then I can help u further.

another this .. I am expecting a reason of all the path "unknow" ... if that's the case please do the following ...

printvar timing_input_port_default_clock

if its false.. then set it to true. and then do the above exercise once again.

 

[dhaval4987]

Birdy, Sure. I will try these out and let you know!

Thanks.

 

[dhaval4987]

Birdy, I did as you said...

report_analysis_coverage -status_details {untested}

gave me the reason 'no_paths' for all the outputs.

Now what next?

 

[birdy123]

Hi,

Now lets try this.. first .. and in the mean time I will see what else you can do ...

> report_disable_timing

it will give u an output like this
Cell or Port From To Sense Flag Reason
---------------------------------------------------------------------
n2_i A Z negative_unate u

1
so from here in the columb Flag , you come to know if any particular timing arc is disabled or not and if yes then what's the reason.

other options and their detail is

Flags : c case-analysis
C Conditional arc
d default conditional arc
f false net-arc
l loop breaking
L db inherited loop breaking
p propagated constant
u user-defined

please try this and copy paste the result. One more thing if you can copy paste the output of report_analysis_coverage -status_details {untested}.. then it will be good.. I wana see what's the string in the PIN columb. Then I can provide you more accurate command to do some testing.

 

[dhaval4987]

Here is the copied result of what you asked.

Hi,
One more thing if you can copy paste the output of report_analysis_coverage -status_details {untested}.. then it will be good.. I wana see what's the string in the PIN columb. Then I can provide you more accurate command to do some testing.

pt_shell> report_analysis_coverage -status_details {untested}
****************************************
Report : analysis_coverage
-status_details {untested}
-sort_by slack
Design : c3540
Version: E-2010.12-SP3
Date : Thu Jun 30 22:54:16 2011
****************************************

Type of Check Total Met Violated Untested
--------------------------------------------------------------------------------
out_setup 22 0 ( 0%) 0 ( 0%) 22 (100%)
out_hold 22 0 ( 0%) 0 ( 0%) 22 (100%)
--------------------------------------------------------------------------------
All Checks 44 0 ( 0%) 0 ( 0%) 44 (100%)


Constrained Related Check
Pin Pin Type Slack Reason
--------------------------------------------------------------------------------
N1713 out_hold untested no_paths
N1713 out_setup untested no_paths
N1947 out_hold untested no_paths
N1947 out_setup untested no_paths
N3195 out_hold untested no_paths
N3195 out_setup untested no_paths
N3833 out_hold untested no_paths
N3833 out_setup untested no_paths
N3987 out_hold untested no_paths
N3987 out_setup untested no_paths
N4028 out_hold untested no_paths
N4028 out_setup untested no_paths
N4145 out_hold untested no_paths
N4145 out_setup untested no_paths
N4589 out_hold untested no_paths
N4589 out_setup untested no_paths
N4667 out_hold untested no_paths
N4667 out_setup untested no_paths
N4815 out_hold untested no_paths
N4815 out_setup untested no_paths
N4944 out_hold untested no_paths
N4944 out_setup untested no_paths
N5002 out_hold untested no_paths
N5002 out_setup untested no_paths
N5045 out_hold untested no_paths
N5045 out_setup untested no_paths
N5047 out_hold untested no_paths
N5047 out_setup untested no_paths
N5078 out_hold untested no_paths
N5078 out_setup untested no_paths
N5102 out_hold untested no_paths
N5102 out_setup untested no_paths
N5120 out_hold untested no_paths
N5120 out_setup untested no_paths
N5121 out_hold untested no_paths
N5121 out_setup untested no_paths
N5192 out_hold untested no_paths
N5192 out_setup untested no_paths
N5231 out_hold untested no_paths
N5231 out_setup untested no_paths
N5360 out_hold untested no_paths
N5360 out_setup untested no_paths
N5361 out_hold untested no_paths
N5361 out_setup untested no_paths
1
pt_shell>

---------- Post added at 07:02 ---------- Previous post was at 06:57 ----------

Also, report_disable_timing showed the following result... nothing matched to what you suggested.

***********************************
pt_shell> report_disable_timing
****************************************
Report : disable_timing
Design : c3540
Version: E-2010.12-SP3
Date : Thu Jun 30 22:58:20 2011
****************************************


1

Kindly help me moving forward. I really appreciate your help birdy.

 

[birdy123]

Hi,

It looks like you havn't link your design properly. or some basic problem.. like setting things..

try following one
> list_designs -all >>>> it should give you design name.. if not then load the design.
>list_libraries >> it should give you all the link libraries.. if it’s not then libraries are not properly linked.

so as per my understanding ... You should follow following procedure. It will help you to debug every thing by your own. So cehck this if you have done this.. If yes then please provide me the feedback for STEP4.

STEP1:
** read the design data***
set search_path
set link_path
read_db
read_verilog
link_design
read_sdf
read_parasitics

NOte1: in your case there is no need of read_sdf and read_parasitic.
NOte2:
The search_path variable specifies a list of directories from which to read the design and library files, so that you do not need to specify a full path each time you read in a file. The link_path variable specifies where and in what order PrimeTime looks for design files and library files for linking the design. For example,

pt_shell> set search_path ". /u/proj/design /u/proj/lib"
pt_shell> set link_path "* STDLIB.db"

Note3: Just use "link_design" in place of "link_design TOP" .. see what will happen...


STEP2:
****constraint the design****
create_clock
set_clock_uncertainty
set_clock_latency
set_clock_transition
set_input_delay
se_out_put_delay

Note:1 you have done this..

STEP3:
*** Specify the environment and analysis conditions***
set_operating_conditions
set_case_analysis
set_mode
read_sdf
read_parasitic
set_driving_cell
set_load
set_wire_load_model
set_multicycle_path
set_false_path
set_disable_timing

Note:1 in your case I think it’s not required....

STEP4: (I think you should do these checking first)
*** check the design and analysis setup***
check_timing >> u have done this in past. SO you can ignore this for the time being.
report_design >> do this and let me know the result. It will give you all the information about ur design
report_port >> all the ports in ur design.
report_net >> this will give you all the result regarding all the nets in your design. I am curious to know the result. You can try one more option after this… “report_net -connections” it will give you all the connections also.
report_cell >> do this .. it will tell u how many cells are present and whether they are connected as per your design. Same here also you can use “report_cell –connections”.
report_wire_load >> you can leave it right now.
report_path_group >> Generates a report on the path groups in the design. PrimeTime organizes timing paths into groups based on the conditions at the path endpoints. Path groups are formed on the bases of capture clock. So in your case if only one clock is present then I think atleast 1 path group should be present.
report_clock >> with the help of this you can check whether everything is correct in terms of clocks. (means u have created a clock .. whether that is created as per ur wishes or not.)
report_hierarchy >> I don’t think its required in ur case.
report_reference >> I don’t think its required in ur case.
report_lib >>if you need the details of ur library then u can use it. Do like this.. first “list_libraries” – it will give you all the linked library .. and then choose any of these and use command .. “report_lib <name of lib>”

Note:1 if you can provide me the output of above command .. it will be good. It will be easy for me to understand your design and the problem.

STEP5:
***Perform a full analysis and examine the results***
report_timing
report_constraint
report_bottleneck
report_analysis_coverage
report_delay_calculation
update_timing

Note:1 There is no need to this right now. You have done this in the past and as per my understanding, it will not help you right now. Because these commands are generally uses in that case when there is any violation but in your case everything is untested. 

 

[dhaval4987]

Birdy,

Sorry I was sick for a few days so could not work and respond to you.. Here are the results.

When I list_libraries, it correctly shows that lib_typical.db is linked. Step 1 and Step 2 are successfully done. Step 3 is not needed in my case and in Step 4- report_port, report_nets and report_cell perfectly reports the design ports and cells. All I found confusing is as below...

pt_shell> report_design
****************************************
Report : design
Design : c3540
Version: E-2010.12-SP3
Date : Tue Jul 5 19:03:59 2011
****************************************

Design Attribute Value
---------------------------------------------------------------------------
Operating Conditions:
analysis_type on_chip_variation
operating_condition_min_name <nominal>
process_min --
temperature_min --
voltage_min --
tree_type_min balanced_case

operating_condition_max_name <nominal>
process_max --
temperature_max --
voltage_max --
tree_type_max balanced_case

Wire Load: (use report_wire_load for more information)
wire_load_mode top
wire_load_model_max --
wire_load_model_min --
wire_load_selection_group_max --
wire_load_selection_group_min --
wire_load_min_block_size 0

Design Rules:
max_capacitance --
min_capacitance --
max_fanout --
max_transition --
max_area --

Timing Ranges:
early_factor --
late_factor --

Pin Input Delays:
None specified.

Pin Output Delays:
None specified.
Fast Analysis: disabled

1

----------------------------------------------
pt_shell> report_path_group
****************************************
Report : path_group
Design : c3540
Version: E-2010.12-SP3
Date : Tue Jul 5 19:05:48 2011
****************************************

Path_Group Weight From Through To
--------------------------------------------------------------------------------
**async_default**
1.00 - - -
**clock_gating_default**
1.00 - - -
**default** 1.00 - - -
MCLK 1.00 * * MCLK

1
-----------------------------------------------

pt_shell> report_lib lib_typical.db
Warning: Nothing implicitly matched 'lib_typical.db' (SEL-003)
Error: Nothing matched for lib (SEL-005)
0
(???)

As I mentioned, the lib_typical.db is successfully linked.
------------------------

Please help.

---------- Post added at 03:34 ---------- Previous post was at 03:15 ----------

Is it because I am not reading sdf file? read somewhere that sdf files are mandatory. If i need those then how do i generate it?

 

[Yanxiang Huang]

I am sure the thread author do not need it any more. But in case any other body need this, e.g. me for the past 3 hours, I post my solutions.

I have exactly the same problem here, it turned out to be that: during link, it cannot find the component from library. So black boxes are refereed.

Although I also tried
read_lib
like the author, it does not help. Very strange.

Finally What saves me is the combination of:

set link_path {* library.db}
link

The the timing report is correct.

Hopefully it helps.