I'm beginner at VHDL and I was trying to implement a 4 bits Register, but I have no idea of how to do it. The code below is what I got at this moment:
Code:
library ieee;
use ieee.std_logic_1164.all;
entity Register4Bits is
port ( D0, D1, D2, D3 : inout std_logic;
WR : in std_logic ); -- W = 0 , R = 1
end Register4Bits;
architecture archRegister4Bits of Register4Bits is
begin
WriteRead : process ( WR )
begin
if WR'event and WR = '1' then
elsif WR'event and WR = '0' then
end if;
end process;
end archRegister4Bits;
for a register you need a clock. the code you have written is treating the WR signal as if it is a clock using both edges, which is not supported in FPGAs.
You need to follow the following code template for registers.
Code:
entity reg is
port (
clk : in std_logic;
d : in std_logic;
q : std_logic
);
architecture rtl of reg is
begin
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;