Help me write a VHDL code for a down counter

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity dcounter is
  
  port (
    rst   : in  std_logic;
    clk   : in  std_logic;
    ld    : in  std_logic;
    din   : in  std_logic_vector(7 downto 0);
    pulse : out std_logic);

end dcounter;

architecture behave of dcounter is
signal count : std_logic_vector(7 downto 0);
signal count_nx : std_logic_vector(7 downto 0);
begin  -- behave
with (count_nx /= "00000000" and count = "00000000") select
  pulse <= '1' when true,
           '0' when others;

  process (clk, rst)
  begin  -- process
    if rst = '1' then                   -- asynchronous reset (active high)
      count <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count_nx;
    end if;
  end process;

  process (count, ld)
  begin  -- process
    if ld = '1' then
      count_nx <= din;
    else
      count_nx <= count - 1;
    end if;
  end process;
end behave;