I am writing VHDL code for one application. In that application, Two 8-bit Registers and one 16-bit Counter will be there. The Counter is a DOWN counter.
The Register is loaded from external 8-bit Micro Processor(MP) and each Register is referenced with a separate address.
When ENABLE pulse is given to a counter, it is loaded(asynchronous) with the registers(8-bit + 8-bit) data at the same time and the counter decrements on rising edge of the clock.
Please anybody help me to write code for the above application.
You can try to use template of ISE, you can find counter and register, I don't understand how your application work, but I think if you have counter and register codes it will be ok.
Hi balakrishna,
can you provide a small waveform (with clock, load signal) so that I can see when the counter is loaded? Put all the signals you are planning to use. If possible define your states-machine for the counter, having this, it will be simple to do the vhdl code.
Is the load signal asynchronous?
What will happen if the counter is already counting and the load signal is asserted?