Help me with DRC error in Calibre

[miladezamani]

Can anyone help me about some drc error such as :
pp.en => enclosure of p0 > 20um
lup.3p => nwell pick up od to pmos space > 30um
and error of empty area of chip?

im doing layout of 6t sram. is it necessary to pass whole of drc rules for sram ??

 

[birdy123]

hi,
As such there is no need to pass whole DRC rules. as you are saying about the empty area of the chip .. so can you check the GDS layer no in that.

another thing .. what's the format of Design database?

 

[miladezamani]

hi,
As such there is no need to pass whole DRC rules. as you are saying about the empty area of the chip .. so can you check the GDS layer no in that.

another thing .. what's the format of Design database?

Thank you for replying. Im working with 90nm tec and i ignored some drc error such as %error. but when i competed the whole design there are errors like the errors when firstly i place a default nmos of cadence. the error = M.1.A & M.2.A> something Which say that the area of metals should be greater than something!!! and LUP error as said before. :sad:

 

[birdy123]

Hi,

You are right. Actually the thing is .. there is no need to load all the DRC at the same time .. but there is also one important thing.. that you have to satisfied all the rules at the end of the day.

One think is .. it looks like the error is because of metal density. Have you done the metal filling?

 

[miladezamani]

Hi,

You are right. Actually the thing is .. there is no need to load all the DRC at the same time .. but there is also one important thing.. that you have to satisfied all the rules at the end of the day.

One think is .. it looks like the error is because of metal density. Have you done the metal filling?

TNX for replying so fast.
How can i do the metal filling?
and also what should i do for below errors?
pp.en => enclosure of p0 > 20um
lup.3p => nwell pick up od to pmos space > 30um

 

[birdy123]

Hi,

This is the error message what you are getting from caliber run. As you have mentioned that you are using 90nm, the best practice for knowing the DRC rule detail is DRM manual. It will give you both the pictorial explanation and also other details also.

some how I have a DRC of 90nm (may be it will help you to understand the rule first). Just wanted to know it can very from foundry to foundry.. But I think you are using TSMC. (anyways below explanation is general).

pp.en => enclosure of p0 > 20um

Mean:
#this is a POLY rule.
# its taking about the encloser of PO.
# in the DRM, you can see that the rule explanation is something like this.. "{NP OR PP} enclosure of PO (except DPO)" >0.20.
# means the distance between the boundry of NP/PP and PO (POLY) should be greater then 0.20.
# trying to capture the pictorial view here... outside one is NP/PO and inner one is PO.. so they are talking about the difference in the boundry. may be a pictorial view can give you a good picture. CHeck DRM.


******************
* *
* *********** *
* * PO * *
* ********* * *
* *
*****************

second rule is related to LAtchup. Again check the DRM for more explanation.

A last note: if you are getting these error.. means your Starndard cell or macros .. basic structure itself. If you have designed that .. then please correct it. else you can talk to Standard cell provider.

One mor ething sometime it may also happen that because of some wrong layer defination you are getting this error. Means you PO GDS layer no is 32. and M1 GDS is 42. but during conversion from one format to other you always use MApping File which Map GDS layer to your database corresponding layer. So it may happen that somehow ur mapping file .. mapped
32 -> 21 (PO)
42 ->21 (PO)

Now during DRC everything is PO. And you may get these violation.

So better cehck all this possiblities.

 

[miladezamani]

Hi,

This is the error message what you are getting from caliber run. As you have mentioned that you are using 90nm, the best practice for knowing the DRC rule detail is DRM manual. It will give you both the pictorial explanation and also other details also.

some how I have a DRC of 90nm (may be it will help you to understand the rule first). Just wanted to know it can very from foundry to foundry.. But I think you are using TSMC. (anyways below explanation is general).

pp.en => enclosure of p0 > 20um

Mean:
#this is a POLY rule.
# its taking about the encloser of PO.
# in the DRM, you can see that the rule explanation is something like this.. "{NP OR PP} enclosure of PO (except DPO)" >0.20.
# means the distance between the boundry of NP/PP and PO (POLY) should be greater then 0.20.
# trying to capture the pictorial view here... outside one is NP/PO and inner one is PO.. so they are talking about the difference in the boundry. may be a pictorial view can give you a good picture. CHeck DRM.


******************
* *
* *********** *
* * PO * *
* ********* * *
* *
*****************

second rule is related to LAtchup. Again check the DRM for more explanation.

A last note: if you are getting these error.. means your Starndard cell or macros .. basic structure itself. If you have designed that .. then please correct it. else you can talk to Standard cell provider.

One mor ething sometime it may also happen that because of some wrong layer defination you are getting this error. Means you PO GDS layer no is 32. and M1 GDS is 42. but during conversion from one format to other you always use MApping File which Map GDS layer to your database corresponding layer. So it may happen that somehow ur mapping file .. mapped
32 -> 21 (PO)
42 ->21 (PO)

Now during DRC everything is PO. And you may get these violation.

So better cehck all this possiblities.

Again TANX a lot. all things you said are correct and i corrcted most errors. i design a 64k sram and when i reached here some error like lup has gone. but the error which is remained is the area errors like area of metal 2 or 1 or poly. how can i fill these layer? for a little altering i must change the whole 64k!!!!

 

[birdy123]

if you are using ICC.. then you can use

insert_metal_fill command.

for other tool check the corresponding command.

if you are in signoff mode.. then you can use metal fill deck provided by foundry.