Help me with a VHDL project with 16 input & output seque

help for vhdl project



we have 16 input(0 to 15).this inputs goes to output Sequence.
2 first bits of per input are priority 2 bit.
Sequences are:
(1)er input that have least of priority 2 bit goes to output sooner(ofcourse in serial mithod).
(2):less input time(it means that for example if 2 input have equal 2 bit priority,Whichever that less
input time goes to output).
(3):less input number(if 2 condition above(1,2) are equal for inputs then per input that have less input
number goes to output).

noticeer input has 2 priority bit in first and 16*8 byte=>130 bit
notice:above 3 conditions and Sequences tests for inputs that its buffer is completed.
notice:we can use ram instead of buffer.
notic:we purpose write behavioral vhdl program.

** this program use quality of servive(Qos)

Re: help for vhdl project

hi,

i don't understand, what is your question exactly?

Re: help for vhdl project

hi,

learn Finite State Machine (FSM) design coding..
merge your design with multiplexer, multipler, and register as well..
the clear concept only comply when you really understand the theory above.
regard
lawrence