hey,im doin my final sem project...i want to know if anyone has the vhdl code to implement fft function on FPGA OR CPLD.
simulation is to be done on MODELSIM
pls help
thanks a tonne
try using megacore for altera or coregenerator for xilinx.it would be simple.
once in place u have the project done, and for better learning process u can start writing ur one code and can even compare the performance.
U cant get any codes from anywhere for ur FFT. Because all codes are different base on ur hardware and hardware version too. It's best to draw out a flowchart and write ur own code. Else if someone gives u the code, and there's problem, u wont be able to solve it.
Using Xilinx ISE 9.1i is a good program. There's a free WEBPack version in www.xilinx.com.
you have started the writing vhdl code for fft processor....
you have to implement butterfly logic...just memory blocks...then
adder block ,multiplyer delay element ...and combine them by behaviour style..
for hoe much tap filter you have chossen???
hi....
as Mr. Swapnil_vlsi told that you have to write code for adder , multiplier and delay element...that is the right flow you can use.....
really it is very easy to do this......