gold_2007
Member level 1
Hi
=>i am given a netlist where the designer has specified PLL present but external mux used to bypass PLL clocks using scan mode setup . what does this signify.
can u elaborate .
=> i ve come across a non scan model TLATNTSCAX2MTH , how do i make it transparent . It has CLK and D input both set to X.
=> i am getting 7809 S1 violation and most of these S1 violation instances come across non scan model TLATNTSCAX2MTH . so what need to be done .
PLEASE REPLY
=>i am given a netlist where the designer has specified PLL present but external mux used to bypass PLL clocks using scan mode setup . what does this signify.
can u elaborate .
=> i ve come across a non scan model TLATNTSCAX2MTH , how do i make it transparent . It has CLK and D input both set to X.
=> i am getting 7809 S1 violation and most of these S1 violation instances come across non scan model TLATNTSCAX2MTH . so what need to be done .
PLEASE REPLY