Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help me understand some DFT violations

Status
Not open for further replies.

gold_2007

Member level 1
Joined
Aug 2, 2007
Messages
40
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
bangalore
Activity points
1,510
Hi

=>i am given a netlist where the designer has specified PLL present but external mux used to bypass PLL clocks using scan mode setup . what does this signify.
can u elaborate .
=> i ve come across a non scan model TLATNTSCAX2MTH , how do i make it transparent . It has CLK and D input both set to X.

=> i am getting 7809 S1 violation and most of these S1 violation instances come across non scan model TLATNTSCAX2MTH . so what need to be done .

PLEASE REPLY
 

alok_msh

Junior Member level 3
Joined
May 1, 2007
Messages
27
Helped
10
Reputation
20
Reaction score
4
Trophy points
1,283
Activity points
1,429
Re: dft violations

If the input clock to TLATNTSCAX2MTH is X then the problem is somewhere downstream. If TLATNTSCAX2MTH drives the clock you need to make sure that in shift/capture mode it is able to drive clock. You might need some changes in netlist.
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

Nithyanantham

Newbie level 2
Joined
Feb 5, 2007
Messages
2
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,281
Activity points
1,292
Re: dft violations

==>As you have mentioned in your design external mux is provided. External mux is used to bypass the PLL clock & test clock will be provided to the design. For transition you have to use PLL clock for capture. For stuck-at you can use test clock.

==>Ensure the model is flop or latch. S1 indicates that whether DFTA is able to change the sequential cell to scannable one

==>Since u have got around 7000 violataions try to put a mux in the downstream(Upper level hierarchy) to resolve s1. Don't let the tool to put the muxes.
 

    gold_2007

    Points: 2
    Helpful Answer Positive Rating

gold_2007

Member level 1
Joined
Aug 2, 2007
Messages
40
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,286
Location
bangalore
Activity points
1,510
Re: dft violations

Nithyanantham said:
==>As you have mentioned in your design external mux is provided. External mux is used to bypass the PLL clock & test clock will be provided to the design. For transition you have to use PLL clock for capture. For stuck-at you can use test clock.

==>Ensure the model is flop or latch. S1 indicates that whether DFTA is able to change the sequential cell to scannable one

==>Since u have got around 7000 violataions try to put a mux in the downstream(Upper level hierarchy) to resolve s1. Don't let the tool to put the muxes.

"Since u have got around 7000 violataions try to put a mux in the downstream(Upper level hierarchy) to resolve s1". Don't let the tool to put the muxes. u mean to say in post scan netlist or prescan netlist .
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top