help me to use a DLL in sparatnII

[Zerox100]

Hi my friends,
i want to use a dll in my design. I can manually do that after place and route, but i want to do that before placeand route. Can anybody help me?

 

[wasp]

Look at : XAPP174,XAPP132.
And for hdl usage look at Design Templates and examples.
Or specify a question.

 

[Zerox100]

I want to specify for Ise that use a DLL in my clock path when i write rtl code

 

[edavio]

instance a DLL in your RTL design. After then, ISE can handle it. DLL is special resource. It can not be generated by synthesizor. Use DLL as a instance in your RTL and don't forget set systhesis attribute as "dont_tuch". Applying DLL instance is done by HDL wrap which xilinx provides.

 

[Zerox100]

instance a DLL in your RTL design. After then, ISE can handle it. DLL is special resource. It can not be generated by synthesizor. Use DLL as a instance in your RTL and don't forget set systhesis attribute as "dont_tuch". Applying DLL instance is done by HDL wrap which xilinx provides.

Have you got an example code?

 

[wasp]

For example:
Look at : Language Templates -> VHDL -> Component Instantiation ->
-> Clock DLL (in XILINX ISE )
Or get it...( it's direct copy & paste from "Language Template" )


--Virtex CLKDLL instantiation
--See XAPP 132 for more examples
--Use "CLK" as your internal clock signal

-- CLKIN_P, RST : in std_logic;
-- LOCKED : out std_logic

--**Insert the following between the 'architecture' and
---'begin' keywords**

signal CLKIN, CLK, CLK0 : std_logic;

component CLKDLL
port (CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;

component IBUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;

component BUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;

--**Insert the following after the 'begin' keyword**
U1: IBUFG port map (I=>CLKIN_P, O=>CLKIN);

U2: CLKDLL port map (CLKIN=>CLKIN, CLKFB=>CLK, RST=>RST,
CLK0=>CLK0, LOCKED=>LOCKED);

U3: BUFG port map (I=>CLK0, O=>CLK);

*****************************************************
For Synplify use syn_black_box attribute for each component.
For other syntez program look documentation...

 

[edavio]

Just follow what wasp said. Otherwise you can pm to me.