For example:
Look at : Language Templates -> VHDL -> Component Instantiation ->
-> Clock DLL (in XILINX ISE )
Or get it...( it's direct copy & paste from "Language Template"
)
--Virtex CLKDLL instantiation
--See XAPP 132 for more examples
--Use "CLK" as your internal clock signal
-- CLKIN_P, RST : in std_logic;
-- LOCKED : out std_logic
--**Insert the following between the 'architecture' and
---'begin' keywords**
signal CLKIN, CLK, CLK0 : std_logic;
component CLKDLL
port (CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
component IBUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
component BUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
--**Insert the following after the 'begin' keyword**
U1: IBUFG port map (I=>CLKIN_P, O=>CLKIN);
U2: CLKDLL port map (CLKIN=>CLKIN, CLKFB=>CLK, RST=>RST,
CLK0=>CLK0, LOCKED=>LOCKED);
U3: BUFG port map (I=>CLK0, O=>CLK);
*****************************************************
For Synplify use syn_black_box attribute for each component.
For other syntez program look documentation...