help me to evaluate the transient current of metal

[liucheng311]

help me with the transient current problem

hello everyone
i am new on power management IC design,and i am confronted with a problem:according to the process application note,the maximum current density of metal2 is 3.5mA/um,how wide should i draw for metal2 if transient current which last 100ns flowing through it is 600mA?

 

[liucheng311]

Re: help me with the transient current problem

anyone help ? please

 

[dick_freebird]

That Met2 must be pretty thick. You can target 1E5 A/cm2 as a survivable DC
current and use the same for time-averaged unidirectional current. A one-time
or very sparse pulse limit (sub-1uS, sub-10%) of 1E6 A/cm2 is reasonable.

More than process application notes, the foundry somewhere has a hard set
of electromigration groundrules for you to obey which should cover these and
the reversing-AC case as well.

 

[tsvetelin_velkov]

or ask your senior design engineer / lead design engineer IC design is not very common topic, I guess no one in the forum is familiar with your process specification and design rules

 

[liucheng311]

thank you, dick_freebird
according what you said, the 17um-width thick metal2(maximum current density is 3.5mA/um) can meet the need of 600mA current pulse(sub-1us),am i right?

 

[dick_freebird]

I/(w*t)=J

I'd say it's close. Probably OK at temperatures below 125C.
Depends some on the assumptions about linewidth reduction
(notching, overetch) which might make the mA/um rule
overly conservative for wider traces, and how your layout
topography's thickness effect on the metal relates to the
structure from which rules are derived (best practive there
is a worst case step, which your real layout ought to avoid
creating).

Now you still need to ensure you respect the time-averaged
current density limit (~60mA, 17um).

Now this linewidth is well less than any sane bond pad so
you might not need to go to minimum for any density interest.
Lines that are up against current density limits tend to be
contributing meaningful series resistance.

In a high current DC-DC I see interconnect drops being
about half of total switch on resistance, and this is with
a whole lot of bond pads in the core and 2-mil wire.
Minimum metal may be interesting from a rules point of
view, but it is not necessarily the right answer for the
product performance (conduction losses, here).

 

[liucheng311]

thank you ,dick_freebird
you helped me a lot.about my last question,i forgot to told you that the time averaged current is less than 0.1mA(so it can be ingored).
and i have another question:where can i find the hard set of electromigration groundrules you talked about? i read all the documents from the
foundry xFAB,and i didnot find it