I/(w*t)=J
I'd say it's close. Probably OK at temperatures below 125C.
Depends some on the assumptions about linewidth reduction
(notching, overetch) which might make the mA/um rule
overly conservative for wider traces, and how your layout
topography's thickness effect on the metal relates to the
structure from which rules are derived (best practive there
is a worst case step, which your real layout ought to avoid
creating).
Now you still need to ensure you respect the time-averaged
current density limit (~60mA, 17um).
Now this linewidth is well less than any sane bond pad so
you might not need to go to minimum for any density interest.
Lines that are up against current density limits tend to be
contributing meaningful series resistance.
In a high current DC-DC I see interconnect drops being
about half of total switch on resistance, and this is with
a whole lot of bond pads in the core and 2-mil wire.
Minimum metal may be interesting from a rules point of
view, but it is not necessarily the right answer for the
product performance (conduction losses, here).