die size 65nm + gate count
aravind:
what ami telling I accept.
u have to sit with fab guys or ask datasheet for that particular technology about Die Sizing.
now other way u cant calculate urslen.
nandgate calculcation wont help u lot.
it will give appr. value.
u have consider lot more than that.
power , temp, SI issues for density of cells.
Well aravind, we are interested in finding the approx value only... the perfect value can be found at the later stage of PD, but while quotation, we have to tell the customer about an approximate size of the die. For this reason mainly, you need to do a die-size estimation. Even customers are appreciating companies those are giving this details before even starting the project. So without design (i.e. before getting the gate count) you have to give the quotation on the die-size. At this time you can't consider power, temp, SI issues for that chip. That's why I told the process of die-size estimation is also depends on the previously achieved data (and of course on the details from fab and the depth of experience).
1. Find out major design blocks (bus architecture, functional IP blocks like 802.11.. etc)
2. Get from your previous project database the module area of those.
3. From the fab guys get the NAND size, and get the details of the scan and non scan flops.
(of course other things has to be considered/assumed like scan flops mostly used, clk buffers mostly used, ScanEnable HFN percentage, Async Reset HFN percentage, Scan Chain Hold Fix percentage, Functional path Hold Fix percentage etc.)
4. With these details, consider both combinational and non-combinational area (as ami said) [but the net interconnect area can not be incorporated in the estimation at these much early stage,.... to some extend it is covered as we took the module area from previous projects]
and remember aravind, there are some companies those are using this method... so u can't say that I can't calculate the die-size with this method. People are using this method and that's why I am providing the information on this.
and yes ami, the size of the NAND should be in mm2