there is nothing called ethernet decoder ! there is ethernet MAC or PHY.
An Ethernet MAC can be implemented in FPGA, you can implement a 10/100base-T enthernet using FPGA "large one" and a PHY.
A PHY can be implemented in high end FPGA for gigabit ethernet "Virtex-II PRO, Virtex II ProX"
Niether of them "PHYor MAC" can be implmented in one CPLD with the current technology.
Designing TCP/IP stack in VHDL is not trivial, usually only MAC layer is done in HDL and TCP/IP in software (also available for 8 bit micros: for eg. uIP).
MAC layer does not need very big FPGA, I've designed fully functional MAC controller full/half duplex 10/100M speed that fits in 600-700 Virtex slices.