[SOLVED] Help me to code Parallel MAC unit in verilog.

[gstekboy]

My parallel MAC unit design is given below.


I have codes for accumulator , booth encoder..etc

Now problem is how to combine this in parallel? can anyone help.

ieee paper is attached below.

View attachment 05337888_2.pdf

 

[Miralipoor]

you can combine your base module by using vhdl.

 

[gstekboy]

you can combine your base module by using vhdl.

Sorry , I would like to continue my work in verilog.

 

[ads-ee]

Now problem is how to combine this in parallel? can anyone help.

What do you mean by combine in parallel? Do you mean you want to implement the partial product summation as a parallel implementation? If so then expect the design to have a very low clock period. The design should be done as the block diagram shows and Fig3 Proposed arithmetic operations shows, using a pipeline registers between blocks and registering the the partial product summation accumulation.

 

[Miralipoor]

you can write your code in any HDL language it does not matter in which language you implement it.
Yes ads-ee is right.To get appropriate clock frequency you must form a pipeline based on your design.