module dig_cntrl_osc(enable, DCO_CONTRL, DCO_OUT);
input enable;
input [7:0] DCO_CONTRL;
output DCO_OUT;
not invsel0( CONTRL6b, DCO_CONTRL[6] );
not invsel1( CONTRL7b, DCO_CONTRL[7] );
and andsel0( sel0, CONTRL7b, CONTRL6b );
and andsel1( sel1, CONTRL7b, DCO_CONTRL[6] );
and andsel2( sel2, DCO_CONTRL[7], CONTRL6b );
and andsel3( sel3, DCO_CONTRL[7], DCO_CONTRL[6] );
nand nandout( DCO_OUTB, cell1_out, enable );
not INV1( DCO_OUT1B, DCO_OUTB );
bufif1 tmp1 (DCO_OUTBs0, DCO_OUTB, enable);//
bufif1 tmp2 (DCO_OUT2Bs1, DCO_OUT2B, enable);//
bufif1 tmp3 (DCO_OUTBs2, DCO_OUTB, enable);//
bufif1 tmp4 (DCO_OUT1Bs3, DCO_OUT1B, enable);//
bufif1 buf1( cell1_in, DCO_OUT1Bs3, sel3 );
bufif0 buf2( cell1_in, cell2_out, sel3 );
bufif1 buf3( cell2_in, DCO_OUTBs2, sel2 );
bufif0 buf4( cell2_in, cell3_out, sel2 );
not INV2( DCO_OUT2B, DCO_OUTB );
bufif1 buf5( cell3_in, DCO_OUT2Bs1, sel1 );
bufif0 buf6( cell3_in, cell4_out, sel1 );
bufif1 buf7( cell4_in, DCO_OUTBs0, sel0 );
not INV3( DCO_OUT, DCO_OUTB );
DCO_CELL cell1( DCO_CONTRL[5:0], cell1_in, cell1_out );
DCO_CELL cell2( DCO_CONTRL[5:0], cell2_in, cell2_out );
DCO_CELL cell3( DCO_CONTRL[5:0], cell3_in, cell3_out );
DCO_CELL cell4( DCO_CONTRL[5:0], cell4_in, cell4_out );
endmodule