help me problem in optimization process

[sarmad88]

help me to solve problem in optimization process

hi
why when i use type array signal with initial value in my code the utilization summary (number of slices ) become 0%
please how can overcome this problem?????
Is there a way to stop the optimization process in ISE14.1??????????? Because it trimmed many important signals system and this signal no appear when make modify conection in chipscope program to debug the signal
please any one help me to overcome this problem

 

[ads_ee]

either use (* keep = "true" *) in front of the signal declaration (for verilog) or the equivalent attribute statement in VHDL to tell ISE to not optimize the signal away. The other option is to turn off trimming of loadless signals, which could have adverse effects on resource utilization.

 

[sureshaa]

You can edit in synthesis preferences also. But it is not recommendable.until or unless you didnt used a signal well, it wont get trim by tool. Because In your post itself you have mentioned all are important signal.
One more point when you are going to use chipscope, please check you have selected soft synthesis. in that time also, it will trim like this.

 

[ads_ee]

sarmad88,

You could instantiate the CS cores in your design and selectively compile them with some debug switch. In verilog I typically just put an:

---

Code Verilog - [expand]
1
2
3
`ifdef CS_DEBUG_MODULE
    // CS instantances go here
 `endif

---

This way I can enable disable useful debug code when I need to check stuff in the lab.

 

[permute]

You really should look into why the signals were trimmed -- normal reasons like "equivalent register removal" or register-balancing/retiming are ok. bad reasons like "unconnected output" or "tied to constant" or "equivalent to register that is also constant" indicate some issue in the HDL. often a missing clock/reset, incorrect reset polarity, or unconnected outputs of some module.