1. The gain from bias3 to OUT will be higher than it is from bias2. From bias2., it is a source degenerated CS amplifier and the degeneration is so high that OUT is insensitive to bias2. But bias 3 has two parallel impedance contributions to it's source degeneration. So if all the conditions for all the transistors being same, you could expect 6dB gain difference. If that is more it tells that the impedance is dominated by the input transistors' channel length modulation. Check M13 and M14
But before all this first check whether all transistors are properly biased and have sufficient margins above vdsat. So much of sensitivity can only come from poor bias margins.
2. No good design can have so much of dependence on bias