To implement the functionality you described, you can follow the here after steps:
1- Detect the input edges (falling and rising).
2- If a falling edge occurs then start counting, if it's a rising edge then reset the counter.
3- The output is keept 1, until counter reaches 12, then it goes low.
If you need more details on how to detect edges, how the hold the value of output without using a latch, or how to implement the counter, then ask and I will follow with you.
I don't understand the words "keeps on set and reset".
Assuming you want a synchronous design, here's some Verilog.
While 'in' is high, load a 5-bit counter with -12. While 'in' is low, count up until the MSB changes to 0. Output the MSB.
Code:
module top (clk, in, out);
input clk, in;
reg [4:0] count = -12;
output out;
assign out = count[4];
always @ (posedge clk)
count <= in ? -12 : count + count[4];
endmodule
I don't understand the words "keeps on set and reset".
Assuming you want a synchronous design, here's some Verilog.
While 'in' is high, load a 5-bit counter with -12. While 'in' is low, count up until the MSB changes to 0. Output the MSB.
Code:
module top (clk, in, out);
input clk, in;
reg [4:0] count = -12;
output out;
assign out = count[4];
always @ (posedge clk)
count <= in ? -12 : count + count[4];
endmodule
If 'in' is not synchronous with 'clk', then my counter example could malfunction due to setup/hold violation of the counter flip-flops. One simple remedy would be to pass 'in' through a clocked D-flop. However, that would increase the latency of the 'in' input, so you may need to modify the overall project to accommodate the extra delay.