design_oriented
Advanced Member level 4
Hi Guys,
I am simulating a VCO with the following design:
Process: 0.18 um
Tool: Cadence Spectre
Topology:Three stage Differential amplifier (with symmetric load)
Supply: 3.3V
Frequency: 2.4GHz
I measured the phase noise and it was -100 dbc/Hz at 10 MHz. Is this a good performance? I am using a DC control voltage of about 875 mV. How can I make the performance better? Can I change the width of the PMOS and NMOS to improve the performance?
Thanks.
I am simulating a VCO with the following design:
Process: 0.18 um
Tool: Cadence Spectre
Topology:Three stage Differential amplifier (with symmetric load)
Supply: 3.3V
Frequency: 2.4GHz
I measured the phase noise and it was -100 dbc/Hz at 10 MHz. Is this a good performance? I am using a DC control voltage of about 875 mV. How can I make the performance better? Can I change the width of the PMOS and NMOS to improve the performance?
Thanks.