Yes, 20V peak to peak, so 10V amplitude, which is much less than the device is rated.You say in your second paragraph that you are putting 20V p-p on the gates (although you later say peak gate voltage is less than that).
Yes, the VGS doesn't really change at all due to different loading or different supply voltage. It never goes above 12V.It sure SOUNDS like you are damaging the gate of the device. Perhaps there's some parasitic capacitance that's causing the VGS to exceed 20V. Have you looked at Vgs with a scope?
I don't think I have the resources (chemicals, microscope, etc) necessary to really inspect the device dies. And I'm not really sure what I'd look for anyways.Have you cracked a failed FET open to see where and what the failure was?
It might require dissolving the plastic depending on the part; on the old Motorola J-Zero packages in the past is was just a matter of heating the package and the ceramic cap would come off to examine the failure (like bond wire pop or small explosion in the base-emitter area).
From the sounds of it, you might have violated Gate-Source breakdown voltage limits.
Jim
Okay, so the rising edge is around 2.5V/ns, and the reverse transfer capacitance is 4.5pF according to the datasheet, so that gives about 11.5ma from drain to gate. The impedance at the gate is <50ohms, so that could only induce about 0.1V of extra voltage. Even with some series inductance the induced voltage won't be very high. And that rising edge occurs right around when the device enters cutoff (Vgs is between 1-2V), so it would take a huge kick to kill the gate at that time. I don't see it happening.Is it possible you're getting some inductive kick from those 1.5uH devices? That could be coupled through the drain-gate capacitance. (And keep in mind, frequency has nothing to do with it, it's edge-rate)
As I said the FET is a MRF1518. The datasheet is here: **broken link removed**L3 220 n ???
what is the fet model ?
They do have diodes but they shouldn't be used in this topology, since the switches only conduct when Vgs is high.u will need diodes on l1 l2 or checkout if the fets have internal diodes.
The forum attachment manager doesn't seem to like .asc files....i assume u want to pass current thru load r1, so what kind of pulse u expect to get on r1 ?
if u know ltspice send the asc file .
No, not really. The supply chokes are not coupled together, and are just meant to supply a roughly constant current to the amplifier drains.index
that's what u are really doing ?
No, this doesn't happen because during turn off the current in the inductor is diverted into the drain-source capacitor, which leads to soft switching behavior. Of course there is internal inductance inside the FET, but there is also internal capacitance, which means the slew rate, and the peak voltage, at the drain is well defined, and should be well within the device capabilities.What rising edge are you refering to? I'm thinking, you've got some current flowing through the 1.5uH, and then you turn off the MOSFET.
V=L *di/dt.
Let's say you've got 10V across that 50 ohms-->200mA. Now, say that fet turns off in 2 nS (I'm just throwing numbers out). That means you've got:
V=1.5uH*0.2/2ns=150V. !!
Even if the FET turns off in 20nS, you're going to get a 15V spike. I'm just sayin'. (This is the kind of situation where you might not see the effect because your scope probe kills it).
Putting the resonant capacitors in parallel with the 220nH inductor does work well in theory, but in practice this gives rise to undamped resonance between the parasitic drain inductance of the FETs and their drain capacitance. This creates some nasty waveforms. Putting the capacitance in parallel with each drain helps greatly to dampen the ringing.I don't have much experience of this variant of class D but the first thing that jumps out at me looking at your simulation is you have the potential for very high common mode gain around 3MHz. i.e. I'd expect to see a very sharp spike of common mode gain and this could cause problems?
Obviously, your simulation won't demonstatrate this issue because your driving source is perfectly differential but in the real world you could get instabilty at 3MHz?
Can you try fitting your filter capacitance across the 220nH inductor rather than in shunt? i.e. change the 1.7nF caps?
I'm not sure what this does for common mode resonances but you would at least lose the huge spiky common mode gain at 3MHz...
The resonance formed by the 1.5uH chokes and the resonant caps is heavily damped by the load resistance (when the amplifier is driven at resonance, anyways). It's somewhat of a concern when trying to quickly modulate the supply voltage, but I'm only varying it very slowly now, so it shouldn't be a problem; at least not for the FETs.
Correct, when driven with common mode signals (either on the gates of the FETs or on the supply voltage) there will be a resonance there. The reason it's damped by the load, even though the load is differential, not common mode, is that when the FETs are driven at the correct frequency and 180 out of phase (as they should), the load effectively becomes common mode (since it is always shorted to ground at one end). And that dissipation will be proportional to the drain bias voltage, thus making it act like a linear damping function. So long as the FETs are operating, the load will dissipate common mode signals.if you strapped both gates together and drove them from an AC source and did an AC analysis I'd expect to see lots of common mode voltage gain at 3MHz. I don't see how the load can damp this type of gain?
I tried damping resistors and didn't see any difference. It was worth a try though.Hence the suggestion to try the 2200 ohm resistors?
However, I guess you would have seen instability on a scope etc. I was concerned in case your 'real' circuit could squeg at 3MHz. i.e. the problem could be how you couple up the driver circuit because it could introduce a common squeg mode.
Also I'm assuming your RF layout is good with short connections to the 1.7nF caps and the drain/inductors and you are using good quality components.
I'm afraid that's all I can suggest. Good luck
It's important that the FETs are hard switched, that's how you get good efficiency. The bias voltage on the gate doesn't really change how linear the FETs operate, but it does effectively adjust their duty cycle.Ok
Why r u using marginal 1v (min from data ) for gate u may slide into grey area of linear area instead of switch ?
I'm not sure what you're referring to here... are you talking about the gate threshold voltage changing with Vds? And the diodes are not in the circuit because they wouldn't have any effect (unless the circuit was severely detuned).check out vdss value (gate off)is higher than regular vds = 12.5v.. ltspice show u have 27v
di d2 did not understand r they or not in circuit and how ?
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