Help me generate waveforms for a given clock

[novicevlsi]

hi all

please refer the attached document.

can any one suggest the best method of generating d1, d2,d3, d4,d5,d6 waveforms for the given clock at the top.

note that there must not be any glitches in d1-d6 waveforms.
if we use a synchronous counter and try to decode the output with an AND gate we get glitches.

so please can anyone suggest the best method , avoiding glitches , becoz these
d1-d6 waveforms are to be used as clocks for triggering other circuits.


thanks in advance.

praven

 

[bronzefury]

Re: clock design

Does your design only use flops that are triggered by rising-edge clocks?

 

[Thomson]

Re: clock design

Please refer to the discussion about how to design glitch-free 4-muxed clock generation written by me!

You can search it using the name "Thomson"


Good luck!


Thomson

 

[novicevlsi]

Re: clock design

dear bronzefury,

the waveforms d1-d6 are to be used to trigger positive edged flops,

thanks for replying,

praven

 

[bronzefury]

Re: clock design

Hi,

Would this help? Please see attached.

bronze

 

[nand_gates]

Re: clock design

Checkout following verilog code....
I am posting this once again...
Hope this helps!

module sequencer(clk, reset, d1, d2, d3, d4, d5, d6);
   input clk, reset;
   output d1, d2, d3, d4, d5, d6;
   reg [5:0]    shift_pos, shift_neg;

   assign       d1 = shift_pos[0] & shift_neg[0];
   assign       d2 = shift_pos[1] & shift_neg[1];
   assign       d3 = shift_pos[2] & shift_neg[2];
   assign       d4 = shift_pos[3] & shift_neg[3];
   assign       d5 = shift_pos[4] & shift_neg[4];   
   assign       d6 = shift_pos[5] & shift_neg[5];
   
   always@(posedge clk or posedge reset) begin
      if (reset) begin
         shift_pos <= 4'h1;
      end else begin
         shift_pos <= {shift_pos[4:0],shift_pos[5]};
      end
   end

   always@(negedge clk or posedge reset) begin
      if (reset) begin
         shift_neg <= 4'h1;
      end else begin
         shift_neg <= {shift_neg[4:0], shift_neg[5]};
      end
   end
     
endmodule // sequencer

 

[novicevlsi]

Re: clock design

i got the desired waveform,

first flop is preset and all other are cleared

see the attached waveform and the circuit diagram,

the waveform is glitch free

the only problem seems to be linear increase of flops, with each additional timing signal, one more flop is required.

can we design with minimum number of flops(like for 8 timing signals, only 3 flops instead of 8 )


-praven

 

[bansalr]

Re: clock design

This is an output of the Ring counter. To generate 2^n states we need
2^n flip flops.

or go for Johnson counter and decode it

 

[bronzefury]

Re: clock design

novicelsi,

is there a reason why duty cycle has to be 10/50? also, why is flop count an issue? are you running out of room in your chip?