module sequencer(clk, reset, d1, d2, d3, d4, d5, d6);
input clk, reset;
output d1, d2, d3, d4, d5, d6;
reg [5:0] shift_pos, shift_neg;
assign d1 = shift_pos[0] & shift_neg[0];
assign d2 = shift_pos[1] & shift_neg[1];
assign d3 = shift_pos[2] & shift_neg[2];
assign d4 = shift_pos[3] & shift_neg[3];
assign d5 = shift_pos[4] & shift_neg[4];
assign d6 = shift_pos[5] & shift_neg[5];
always@(posedge clk or posedge reset) begin
if (reset) begin
shift_pos <= 4'h1;
end else begin
shift_pos <= {shift_pos[4:0],shift_pos[5]};
end
end
always@(negedge clk or posedge reset) begin
if (reset) begin
shift_neg <= 4'h1;
end else begin
shift_neg <= {shift_neg[4:0], shift_neg[5]};
end
end
endmodule // sequencer