Help me fix my state machine with a counter VHDL code

[akrlot]

hi;
i want to code a state machine with a counter.there's 10 cycles between state k_fv
and k_fo(incerement couter from 0 to 9) and 15 cycles between k_fo and k_fr and
1cycle between k_fr and k_fv. thx in advance.

this is my code but if simulated it doesnt give the wanted result.thx
library ieee;
use ieee.std_logic_1164.all;

entity feu_ctl is
generic(size: integer:=15);
port(clk:in std_logic;
rst_n: in std_logic;
o_fv: out std_logic;
o_fo: out std_logic;
o_fr: out std_logic);
end feu_ctl;

architecture ARCH of feu_ctl is
type feu_state is(k_fv,k_fo,k_fr);
signal feu_fsm_d,feu_fsm_q:feu_state;

signal cpt_q,cpt_d:integer ;
begin
p1: process(clk,rst_n)
begin
if(rst_n='0')then feu_fsm_q<=k_fr ;
cpt_q<=0;
elsif clk='1' and clk'event then feu_fsm_q<=feu_fsm_d ;
cpt_q<=cpt_d;
end if;
end process p1;

p2: process(feu_fsm_q,cpt_q)
begin
if cpt_q=size-1 then cpt_d<=0;
else cpt_d<=cpt_q+1;
end if;
case feu_fsm_q is
when k_fv=> o_fv<='1';o_fo<='0';o_fr<='0';feu_fsm_d<=k_fo;
when k_fo=> if cpt_q=10 then
o_fo<='1';o_fr<='0';o_fv<='0';feu_fsm_d<=k_fr;cpt_d<=0;
end if;
when k_fr=> if cpt_q=1 then
o_fr<='1';o_fv<='0';o_fo<='0';feu_fsm_d<=k_fv;cpt_d<=0;
end if;
end case;
end process p2;
end ARCH;

 

[nand_gates]

Re: vhdl code

here is the corrected code ....

library ieee;
use ieee.std_logic_1164.all;

entity feu_ctl is
  generic(size :     integer := 15);
  port(clk     : in  std_logic;
       rst_n   : in  std_logic;
       o_fv    : out std_logic;
       o_fo    : out std_logic;
       o_fr    : out std_logic);
end feu_ctl;

architecture ARCH of feu_ctl is
  type feu_state is(k_fv, k_fo, k_fr);
  signal feu_fsm_d, feu_fsm_q : feu_state;

  signal cpt_q, cpt_d : integer;
begin
  p1                  : process(clk, rst_n)
  begin
    if(rst_n = '0')then
      feu_fsm_q <= k_fr;
      cpt_q     <= 0;
    elsif clk = '1' and clk'event then
      feu_fsm_q <= feu_fsm_d;
      cpt_q     <= cpt_d;
    end if;
  end process p1;
-- there's 10 cycles between state k_fv
-- and k_fo(incerement couter from 0 to 9) and 15 cycles between k_fo and k_fr and
-- 1cycle between k_fr and k_fv. 
  p2 : process(feu_fsm_q, cpt_q)
  begin
    if cpt_q = size-1 then
      cpt_d <= 0;
    else
      cpt_d <= cpt_q+1;
    end if;

    case feu_fsm_q is
      when k_fv =>
           if (cpt_q = 9) then
             feu_fsm_d <= k_fo;
             cpt_d <= 0;
           end if;
      when k_fo =>
        if (cpt_q = 14) then
          feu_fsm_d <= k_fr;
        end if;
      when k_fr =>
        feu_fsm_d <= k_fv;
        cpt_d <= 0;
    end case;
  end process p2;

-- state machine o/p decoder
  p3: process (feu_fsm_q)
  begin  -- process p3
    case feu_fsm_q is
      when k_fv =>
           o_fv <= '1';
           o_fo <= '0';
           o_fr <= '0';
      when k_fo =>
           o_fo <= '1';
           o_fr <= '0';
           o_fv <= '0';
      when k_fr =>
           o_fr <= '1';
           o_fv <= '0';
           o_fo <= '0';
    end case;
  end process p3;
end ARCH;

Hope this helps!